PLX Technology PEX 8311RDK Hardware Reference Manual

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PEX 8311RDK Hardware Reference Manual

PEX 8311RDK Hardware Reference Manual

Version 0.90 December 2005

Website: Support: Phone: Fax:

http://www.plxtech.com http://www.plxtech.com/support 408 774-9060 800 759-3735 408 774-2169

© 2005 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products. PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc. Other brands and names are the property of their respective owners. Order Number: PEX8311-RDK-HRM-P1-0.90 Printed in the USA, December 2005

CONTENTS 1. General Information ............................................................................................................................... 1 1.1 PEX 8311 Features ......................................................................................................................... 2 1.2 PEX 8311RDK Features.................................................................................................................. 2 2. PEX 8311RDK System Architecture ...................................................................................................... 3 3. PEX 8311RDK Hardware Architecture .................................................................................................. 4 3.1 PEX 8311 PCI Express Bridge Device............................................................................................ 4 3.2 Serial EEPROM ............................................................................................................................... 4 3.2.1 SPI EEPROM............................................................................................................................ 5 3.2.2 Microwire Serial EEPROM........................................................................................................ 5 3.2.2.1 Microwire Serial EEPROM Contents ............................................................................... 6 3.3 Local and PCI Express Hardware Elements ................................................................................... 7 3.3.1 Local Clock................................................................................................................................ 8 3.3.2 Synchronous Burst SRAM ........................................................................................................ 8 3.3.3 Xilinx CPLD ............................................................................................................................... 8 3.3.4 Internal Clock ............................................................................................................................ 8 3.3.5 PLX Option Module Connector ................................................................................................. 9 3.3.6 Hardware Memory Map .......................................................................................................... 10 3.4 PCI Express Interface.................................................................................................................... 10 3.4.1 RefClk ..................................................................................................................................... 10 3.4.2 PERST# .................................................................................................................................. 10 3.4.2.1 Reset Circuitry ............................................................................................................... 11 3.5 LED Indicators ............................................................................................................................... 11 3.6 PEX 8311RDK Power.................................................................................................................... 11 3.6.1 PEX 8311 Bridge Device Power ............................................................................................. 11 3.6.2 PEX 8311 Power Jumpers and Resistor options.................................................................... 12 3.7 Power Management Signaling....................................................................................................... 13 3.7.1 Wakeup ................................................................................................................................... 13 3.8 Endpoint/Root Complex operation ................................................................................................ 13 4. Mechanical Architecture....................................................................................................................... 15 4.1 Monitoring Points, Test headers, Indicators, Control, and DIP Switch Summary ......................... 16 4.1.1 Monitoring Points .................................................................................................................... 16 4.1.2 Headers................................................................................................................................... 16 4.1.2.1 Test Headers ................................................................................................................. 16 4.1.2.2 JTAG Headers ............................................................................................................... 16 4.1.3 Indicators................................................................................................................................. 17 4.1.4 Controls................................................................................................................................... 17 4.2 PEX 8311RDK Layout Information................................................................................................ 17 4.2.1 Trace Routing Design Rules ................................................................................................... 17 4.2.2 Power Decoupling ................................................................................................................... 17 4.2.3 PCB Stackup........................................................................................................................... 18 4.3 MidBus LAI Footprints ................................................................................................................... 19 4.4 Prototyping Area............................................................................................................................ 19 4.4.1 Surface Mount Footprints........................................................................................................ 19 4.4.2 Uncommitted FPGA footprint .................................................................................................. 20 4.4.2.1 Uncommitted FPGA connections .................................................................................. 20 4.4.2.2 Uncommitted FPGA to PEX 8311 local bus .................................................................. 20 4.4.2.3 Programming the uncommitted FPGA........................................................................... 24 4.4.2.3.1 Programming the FPGA through the JTAG interface................................................ 24 4.4.2.3.2 Programming the FPGA through the GPIO ............................................................... 27 4.4.2.3.3 Programming the uncommitted FPGA from the configuration PROM....................... 28 4.4.2.4 Uncommitted FPGA power supplies.............................................................................. 29 4.4.2.5 Uncommitted FPGA Pull-ups/downs ............................................................................. 30 4.4.2.6 Increasing the number of unused uncommitted FPGA I/O ........................................... 30 5. RDK Mode Configuration ..................................................................................................................... 31 6. Examples of Testing the OnBoard 32Kx32 SBSRAM with PLXMon ................................................... 33 7. CPLD Verilog Code.............................................................................................................................. 35 PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

v

7.1 Verilog Code .................................................................................................................................. 35 8. References ........................................................................................................................................... 39 9. Bill of Materials / Schematics ............................................................................................................... 41

FIGURES Figure 1-1. PEX 8311RDK – Component Side View.................................................................................... 1 Figure 3-1. PEX 8311RDK Hardware Architecture ...................................................................................... 4 Figure 4-1. PEX 8311RDK Component Placement.................................................................................... 15 Figure 4-2. PEX 8311RDK Decoupling Capacitor Footprints..................................................................... 18 Figure 4-3. PEX 8311RDK Stackup ........................................................................................................... 18

TABLES Table 3-1. Long Serial EEPROM Load Registers ........................................................................................ 6 Table 3-2. Extra Long Serial EEPROM Load Registers............................................................................... 7 Table 3-3. PEX 8311RDK Processor/Local Bus Memory Map .................................................................. 10 Table 3-4. PEX 8311RDK LED Indicators .................................................................................................. 11 Table 3-5. PEX 8311RDK Power supply currents...................................................................................... 12 Table 3-6. PEX 8311RDK Power jumper and resistor options................................................................... 12 Table 4-1. PEX 8311RDK Default Jumper Settings ................................................................................... 17 Table 4-2. Layer thickness ......................................................................................................................... 19 Table 4-3. Six (6) Surface Mount Footprints .............................................................................................. 19 Table 4-4. Uncommitted FPGA resistor configuration................................................................................ 21 Table 4-5. Altera Uncommitted FPGA JTAG interconnections .................................................................. 25 Table 4-6. Xilinx Uncommitted FPGA JTAG interconnections ................................................................... 26 Table 4-7. Programming the Altera Uncommitted FPGA through the GPIO.............................................. 27 Table 4-8. Programming the Xilinx Uncommitted FPGA through the GPIO............................................... 28 Table 4-9. Platform Flash to Xilinx interconnect......................................................................................... 29 Table 5-1. RDK Board Mode Configuration................................................................................................ 31 Table 9-1. PEX 8311RDK Bill Of Materials ................................................................................................ 41

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PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

PREFACE NOTICE This document contains PLX Confidential and Proprietary information. The contents of this document may not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc. PLX provides the information and data included in this document for your benefit, but it is not possible to entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this information. The information in this document is subject to change without notice. Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental or consequential damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the PEX 8311RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.

ABOUT THIS MANUAL This document describes the PLX PEX 8311RDK, the PEX 8311 Rapid Development Kit, from a hardware perspective. It contains a description of all major functional circuit blocks on the board and also is a reference for the creation of software for this product. This manual also includes a complete bill of materials and schematics.

REVISION HISTORY Date

Version

December 2005

0.90

Comments Initial Blue Book Release

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

vii

1.

General Information

The PLX PEX 8311RDK is a Rapid Development Kit based on the PEX 8311, a single-lane, PCI Expressto-local bus bridge device. The PEX 8311RDK provides a complete hardware and software development platform to facilitate getting designs up and running quickly, lowering risk and reducing time-to-market. The PEX 8311RDK allows the upstream PCI Express port of the PEX 8311 device to be connected to a host system slot by way of a standard PCI Express edge connector (the PEX 8311RDK is designed to plug into a PCI Express motherboard slot). On board Synchronous burst SRAM allows testing of data transfers and DMA operation. The PEX 8311RDK is shipped pre-configured for de-multiplexed generic address/data bus (C mode) operation, but is very easily reconfigured for multiplexed address/data bus (J mode) applications. The RDK provides 5 surface mount QFP/SOIC/SSOP footprints and for hardware designers to easily add processors, DSPs, ASICs, FPGAs, memory, and I/O devices to test, simulate, and debug their designs without fabricating their own boards, saving considerable of time in the development process and reducing time to market. The PEX 8311RDK’s software, hardware and registers are backward-compatible with the PCI 9056RDK-LITE and PCI 9656RDK-LITE, simplifying the migration of existing PCI designs into PCI Express products.

SOIC

SSOP

Prototyping Area

SSOP

FPGA PQFP

SSOP

TP6 LAH2

POM Module Connector

J3 TP7

Test Headers

+5V

+12V

LED 1

JP2

LED 2

JP3

LED 3

JP4

LED 4

JP5

LAH5

LAH3

LAH6

TP10

LAH4 TP9

JTAG Header

TP8 J2

LAH1

5V Power Connector

TP11

SYN_SRAM

CPLD

J4 TP5

Eeprom J9

Socket

TP3

1 J1

JTAG Header

J7

Eeprom

Regulator

U8 TP1 J8

Regulator

U3

PEX8311 PEX-MCM

TP2

JP1

66MHz Oscillator for LocalClock Socket

PEXCLK

U9

LED7 LED6

LED4

1 Socket

Regulator

LED5

U2

U6

U4

U5 J5

PERST#

Midbus

PERST#

TP4

PLX Technology , Inc . PEX8311 RDK COPYRIGHT 2005

Figure 1-1. PEX 8311RDK – Component Side View PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

1

1.1

PEX 8311 Features ƒ

Compliant to PCI Express Base Specification, Revision 1.0a

ƒ

Local bus and register compatibility with PCI 9056 and PCI 9656 allows systems to migrate to PCI Express and leverage software compatibility

ƒ

Integrated single PCI Express port and interface with x1 link, dual-simplex 2.5 Gbps SerDes

ƒ

Configurable local bus supporting 8, 16 and 32 bit local bus architectures

ƒ

Multiplexed and non-multiplexed local bus operation

ƒ

Powerful high performance DMA engine supporting block, scatter gather, ring management and demand mode

ƒ

Supports Endpoint and Root Complex Modes

ƒ

Small package, enabling compact design

ƒ

Low power consumption

ƒ

3.3V I/O and 5V tolerant local bus

ƒ

Serial EEPROMs used for optional boot configuration with Serial Peripheral Interface (SPI) and Microwire Interface

ƒ

8-KB general-purpose shared RAM

1.2

2

PEX 8311RDK Features ƒ

PLX PCI Express-to-PCI bridge device in a 21 x 21 mm, 337-ball PBGA package

ƒ

Single x1 PCI Express Edge connector for insertion into standard PCI Express slot of x1 or greater link width

ƒ

Supports 32-bit C (default) or J mode Processor/Local Bus operation with speeds up to 66MHz

ƒ

128KB synchronous burst SRAM with the CPLD memory controller demonstrates the PEX 8311 continuous burst feature

ƒ

Jumpers for PEX 8311 hardware configuration

ƒ

Socketable SPI and Microwire serial EEPROMs (3.3V devices supported)

ƒ

Onboard probing points and logic analyzer connections

ƒ

LEDs for link status visual inspection and power supply operation

ƒ

Auxiliary ATX hard disk connector for additional power requirement support

ƒ

Prototyping area with five (5) surface mount footprints, one (1) voltage regulator footprint, and one (1) 20x10, 0.1” through-hole grid

ƒ

Pushbutton reset module

ƒ

Socketed oscillator for Processor/Local Bus clock and local logic

ƒ

PLX J-Bus Option Module (POM) connector for expansion

ƒ

Option for on board PCI Express reference clock generation

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

2.

PEX 8311RDK System Architecture

The PEX 8311RDK assists customers in evaluating PLX Technology’s PEX 8311 PCI Express to local bus bridge device, and to facilitate early development of customer designs with the PEX 8311. The board is designed to operate with the PEX 8311 configured in Endpoint mode. This allows bridging between a PCI Express base board and local bus processors or logic. The PEX 8311RDK is designed to showcase many of the PEX 8311 features when operating in Endpoint mode. The PEX 8311RDK’s form factor is a eight-layer assembled 6.6"L x 8.15"W PC board. The local bus interface supports 8, 16 or 32-bit transfers, at up to 66 MHz. The PCI Express interface supports one lane operating at 2.5 Gbps. PEX 8311RDK power is generated from the +12VDC and +3.3VDC, provided through the PCI Express edge connector. Additional +5VDC and +12VDC power can be provided using an external power supply plugged into the on board 4-pin ATX header.

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

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3.

PEX 8311RDK Hardware Architecture PEX 8311 RDK Hardware Block Diagram PCI Express Pushbutton Reset Circuit

POM Connector

x 1 P C I E x p r e s s C a r d E d g e

LED's for GPIO's and power supplies

Prototyping Area & Footprints

Test Headers

Address Bus PCI Express x1 Link

Data bus

PEX8311

Midbus Connector (not populated)

Control Bus 7

Address

Local Clock

8

Data Bus

Controls

PCI Express 100MHz clock

Ready# Bterm#

PCI Express 100MHz Clock Circuit (not populated)

SRAM SRAM Controller Controller Arbiter Chip Select Generator

Serial EEPROMs

Internal Clock Circuit 66MHz (not populated)

Local Bus Clock Circuit 66MHz

LOCAL BUS Up to 32-bit 66MHz

32

Memory Address Bus 8 Controls

Synchronous SRAM 32Kx32

Xilinx CPLD

Figure 3-1. PEX 8311RDK Hardware Architecture 3.1

PEX 8311 PCI Express Bridge Device

The PEX 8311 (U1) is a high-performance PCI Express to local bus device that enables designers to migrate legacy designs to the new, advanced serial PCI Express. This 2-port device is equipped with a single-lane PCI Express port and a parallel local bus segment supporting multiplexed (J mode) and nonmultiplexed (C Mode) operating modes. The PEX 8311 is capable of operating as an Endpoint or a Root Complex. The PEX 8311 bridge device is housed in a 21 x 21 mm, 337-ball PBGA package. Ball spacing is 1.0 mm. No additional cooling is required. The PEX 8311 supports Direct Slave and Direct Master data transfers; in addition there are two DMA channels, and an Intelligent Messaging Unit. For more detailed information about the PEX 8311 please see the PEX 8311 data book.

3.2

Serial EEPROM

The PEX 8311 bridge device has two EEPROM’s associated with it. These EEPROM’s can be used to load configuration data on power-up.

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PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

3.2.1

SPI EEPROM

The SPI EEPROM (U2) is the Express Configuration EEPROM. This is largely used to control PCI Express performance and is not normally required to bring up the PEX 8311. The SPI EEPROM (U2) can also be used to pre-configure the on-chip 8K shared memory. The SPI EEPROM (U2) is connected to an 8-pin DIP socket to allow removal and programming with external PROM programmer if required. The EEPROM can also be programmed through the PEX 8311 using the utilities provided. A pull-up resistor (R4) on the EERDDATA ball produces a value of FFh if there is no serial EEPROM installed. The PEX 8311 supports up to 16 MB SPI serial EEPROM’s, utilizing 1, 2, or 3-byte addressing. The PEX 8311 automatically determines the appropriate addressing mode. The SPI operates at up to 25 MHz and can directly interface with the PEX 8311. The Atmel AT25640 device as used in the PEX 8311RDK is recommended. Other compatible 128-byte serial EEPROM’s include the Atmel AT25010A, Catalyst CAT25C01, and ST Microelectronics M95010W. The SPI EEPROM on the PEX 8311RDK is blank when shipped.

3.2.2 Microwire Serial EEPROM The socketed 2Kbit Microwire serial EEPROM (U6) is the Local Configuration EEPROM and is used to control local bus behavior and assign appropriate address ranges. It is connected directly to the PEX 8311 and provides the configuration data to initialize the device after the system reset is removed. The EEPROM image is compatible with those of the PLX PCI 9x56 devices and may be loaded with those images to speed development. The Microwire EEPROM will be required for most designs to ensure that the correct address space ranges are assigned. A pull-up on EEDI/EEDO (R36) ensures that the RDK will boot if a blank EEPROM is installed. If no EEPROM is installed then a pull-down will be required on EEDI/EEDO (R39) to ensure that the device boots correctly.

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

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3.2.2.1

Microwire Serial EEPROM Contents Table 3-1. Long Serial EEPROM Load Registers

Serial EEPROM Offset 0h 2h 4h 6h 8h Ah Ch Eh 10h 12h 14h 16h

Serial EEPROM Hex Value 86E1 10B5 0680 00AA 0000 0100 0000 0000 0000 0000 FFFE 0000

18h

0000

1Ah

0001

1Ch 1Eh

0120 0000

20h

2030

22h

8500

24h 26h

0000 0000

28h

0000

2Ah

0000

2Ch

4343

2Eh

00C3

30h 32h 34h 36h

0000 0000 6000 0000

38h

5000

3Ah

0000

3Ch

0000

3Eh

0000

40h

0000

42h

0000

6

Description

Register Bits Affected

Device ID Vendor ID Class Code Class Code, Revision of the PEX 8311 Maximum Latency, Minimum Grant Interrupt Pin, Interrupt Line Routing MSW of Mailbox 0 (User Defined) LSW of Mailbox 0 (User Defined) MSW of Mailbox 1 (User Defined) LSW of Mailbox 1 (User Defined) MSW of Range for PCI-to-Local Address Space 0 LSW of Range for PCI-to-Local Address Space 0 MSW of Local Base Address (Re-map) for PCI-to-Local Address Space 0 LSW of Local Base Address (Re-map) for PCI-to-Local Address Space 0 MSW of Mode/DMA Arbitration Register LSW of Mode/DMA Arbitration Register Local Miscellaneous Control Register 2 / Serial EEPROM Write-Protected Address Boundary Local Miscellaneous Control Register 1 / Processor/Local Bus Big/Little Endian Descriptor Register MSW of Range for PCI-to-Local Expansion ROM LSW of Range for PCI-to-Local Expansion ROM MSW of Local Base Address (Re-map) for PCI-to-Local Expansion ROM LSW of Local Base Address (Re-map) for PCI-to-Local Expansion ROM MSW of Bus Region Descriptors for PCI-to-Local Address Space 0 and Expansion ROM LSW of Bus Region Descriptors for PCI-to-Local Address Space 0 and Expansion ROM MSW of Range for Direct Master-to-PCI LSW of Range for Direct Master-to-PCI MSW of Local Base Address for Direct Master-to-PCI Memory LSW of Local Base Address for Direct Master-to-PCI Memory MSW of Processor/Local Bus Address for Direct Master-to-PCI I/O Configuration LSW of Processor/Local Bus Address for Direct Master-to-PCI I/O Configuration MSW of PCI Base Address (Re-map) for Direct Master-to-PCI LSW of Processor/Local Bus Address for Direct Master-to-PCI Memory MSW of PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration LSW of PCI Configuration Address Register for Direct Master-to-PCI I/O Configuration

PCIIDR[31:16] PCIIDR[15:0] PCICCR[23:8] PCICCR[7:0] / PCIREV[7:0] PCIMLR[7:0] / PCIMGR[7:0] PCIIPR[7:0] / PCIILR[7:0] MBOX0[31:16] MBOX0[15:0] MBOX1[31:16] MBOX1[15:0] LAS0RR[31:16] LAS0RR[15:0] LAS0BA[31:16] LAS0BA[15:0] MARBR[31:16] MARBR[15:0] LMISC2[7:0] / PROT_AREA[7:0] LMISC1 [7:0] / BIGEND [7:0] EROMRR[31:16] EROMRR[15:0] EROMBA[31:16] EROMBA[15:0] LBRD0[31:16] LBRD0[15:0] DMRR[31:16] DMRR[15:0] DMLBAM[31:16] DMLBAM[15:0] DMLBAI[31:16] DMLBAI[15:0] DMPBAM[31:16] DMPBAM[15:0] DMCRGA[31:16] DMCFGA[15:0]

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

Table 3-2. Extra Long Serial EEPROM Load Registers Serial EEPROM Offset 44h 46h 48h 4Ah

Serial EEPROM Hex Value 8311 10B5 FFFE 0000

4Ch

0000

4Eh

0001

50h

0000

52h

01C3

54h

0000

56h

4C06

58h 5Ah 5Ch

0000 0000 7A02

5Eh

4801

60h

0000

62h

0000

3.3

Description Subsystem ID Subsystem Vendor ID MSW of Range for PCI-to-Local Address Space 1 LSW of Range for PCI-to-Local Address Space 1 MSW of Local Base Address (Re-map) for PCI-to-Local Address Space 1 LSW of Local Base Address (Re-map) for PCI-to-Local Address Space 1 MSW of Bus Region Descriptors for PCI-to-Local Address Space 1 LSW of Bus Region Descriptors for PCI-to-Local Address Space 1 Hot Swap Control/Status Register Hot Swap Control/Status Register / Hot Swap Next Capability Pointer Reserved PCI Arbiter Control Power Management Capabilities Power Management Next Capability Pointer / Power Management Capability ID (the LSB is reserved) Power Management Data / PMCSR Bridge Support Extensions (the LSB is reserved) Power Management Control/Status (Bits 15, 7:2, and 1:0 are reserved)

Register Bits Affected PCISID[15:0] PCISVID[15:0] LAS1RR[31:16] LAS1RR[15:0] LAS1BA[31:16] LAS1BA[15:0] LBRD1[31:16] LBRD1[15:0] Reserved HS_NEXT[7:0] / HS_CNTL[7:0] Reserved PCIARB[15:4] / PCIARB[3:0] PMC[15:9,2:0] PMNEXT[7:0] / PMCAPID[7:0] PMDATA[7:0]/ PMCSR_BSE[7:0] PMCSR[15:0]

Local and PCI Express Hardware Elements

As shown in Figure 3-1, the RDK hardware contains: • • • • • • •

PEX 8311 PCI Express I/O Accelerator Four PEX 8311 Local Bus components (Local clock distribution, CPLD, SBSRAM, Test Headers, and POM connector) LED’s for GPIO and power supply status Small prototyping area – including an uncommitted FPGA footprint PCI Express Reset Circuitry (see section 3.4.2.1 Reset Circuitry) A hardware development module for PCI Express clock generation (see section 3.4.1 RefClk) A hardware development module for the PEX 8311 internal reference clock (see section 3.3.4 Internal Clock)

The RDK’s Local Bus is pre-configured for non-multiplexed address and data bus operation (C mode), but it is user-configurable to allow multiplexed address and data operation (J Mode). (See Section 5 RDK Mode Configuration for details on re-configuring the RDK hardware for J Mode operation.) Once the board is correctly installed into a PC computer system, a host, such as the motherboard’s processor, can perform single cycle memory read/write cycles, multiple memory read/write cycles, and burst memory read/write cycles from/to the on-board SBSRAM in Direct Slave mode. The host can also program the PEX 8311 to perform DMA data transfers between the PCI Express bus and the SBSRAM.

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

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3.3.1

Local Clock

The PEX 8311 has a local clock input which is required for normal operation. The Cypress Semiconductor CY2305 Zero Delay 1-to-5 clock buffer (U7) provides onboard local clock distribution to the PEX 8311, SBSRAM, CPLD, test headers and the POM connector. The CY2305 input is sourced by the socketed onboard oscillator (U8). The socketed oscillator (U8) can be changed to allow PEX 8311 local bus operation at any frequency from 10 to 66MHz. The 10MHz minimum is a restriction of the CY2305, the local bus of the PEX 8311 can run at any frequency from 0 to 66MHz. 3.3.2 Synchronous Burst SRAM A 100-pin, 7.5ns, 32K x 32 Micron Synchronous Burst SRAM (U11) is used for Processor/Local Bus data storage on the RDK. During Direct Slave memory burst cycles, the SBSRAM performs continuous backto-back single read cycles or single write cycles. The Xilinx CPLD SBSRAM controller (U10) does all of the timing conversion and generates the lower 8 address bits to the SBSRAM. The SBSRAM takes 7 upper address lines (LA16-LA10) directly from the PEX 8311 and 8 lower address lines (MA[9:2]) from the SBSRAM controller. The data lines of the SBSRAM are directly connected to the PEX 8311 local data bus (LD31-LD0). 3.3.3 Xilinx CPLD A 5ns Xilinx XC9572XL-5TQ100C CPLD (U10) is used as the SBSRAM controller, external Processor/Local Bus arbiter, and chip select generator. The SBSRAM controller in the CPLD generates the lower 8-bit memory address (MA[9:2]), SBSRAM chip select (SRAMCS#), SBSRAM output enable (SRAMOE#), and SBSRAM byte write enables (SRAM_BW_[3:0]) to the SBSRAM. It latches the starting address signals (LA[9:2] for C mode and LAD[9:2] for J mode), and uses its built-in internal address counter to advance the addresses to the SBSRAM. The SBSRAM controller also generates the active low ready signal (READY#) to terminate normal PEX 8311 memory cycles and also generates the active low (BTERM#) input to the PEX 8311 to break the continuous burst memory cycle when its internal address counter reaches the final count (FFh). The external Processor/Local Bus arbiter in the CPLD accepts the Processor/Local Bus request signals (LBR [1:0]) from Processor/Local Bus masters, if there are any, and the bus request from the PEX 8311 (LHOLD). It generates bus grant signals LBG [1:0] to the Processor/Local Bus masters and LHOLDA to the PEX 8311. The chip select generator in the CPLD generates the SBSRAM chip select (SRAMCS#) and four additional active low chip selects for the Processor/Local Bus devices. The chip select signals are partially decoded from the upper four address lines (LA31-LA28) on the Processor/Local Bus. They can be re-programmed by altering the CPLD Verilog code. 3.3.4

Internal Clock

The PEX 8311 requires an internal clock source in addition to the PCI Express clock and the local clock. When the PEX 8311 is operating in Endpoint mode the PEX 8311 will generate the internal clock itself. The internal clock output (CLKOUT, ball A8) is fed directly to the internal clock input (CLKIN, ball A15) via the 0 ohm series resistor R53. When the PEX 8311 is operating in Root Complex mode then the internal clock must be provided from an external source. While the PEX 8311RDK is not designed to operate in Root Complex mode provision has been made for an external clock oscillator to provide the internal clock to the PEX 8311. The components for the external clock are not assembled nor do they appear on the BOM. Customers who require this feature must source and assemble the components themselves. PLX takes no responsibility for boards damaged during this operation If the external oscillator is to be used remove R53 and assemble R52, R150, C96, C97 and U13. The maximum operating frequency for U13 should be 66MHz.

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PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

3.3.5 PLX Option Module Connector The PLX Option Module Connector (J3) assumes that the Local Bus is configured for 32-bit multiplexed address/data bus (J mode) operation. (See Section 5 - RDK Mode Configuration - for details on reconfiguring the RDK hardware for J Mode operation.) It can be used for expansion and prototyping. Both/either a master and/or slave devices may be connected to this connector, which resides at Local Bus address range 1000 0000 – 1FFF_FFFFh. The external arbiter in the CPLD uses CS0# to select the POM module. Schematic sheet 6 provides the connector signal details. The connector to mate to J3 can be purchased from AMP distributors the part number is: 6-104652-0

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

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3.3.6 Hardware Memory Map The PEX 8311RDK Local Bus memory map is shown in Table 3-3. Table 3-3. PEX 8311RDK Processor/Local Bus Memory Map Hex Address Range FFFF FFFF 5000 0000

3.4

Device

Chip Select

Comments

Unused

_

Available

4FFF FFFF 4000 0000

Uncommitted FPGA (FP2)

CS3#

Available & Re-programmable

3FFF FFFF 3000 0000

Unused

CS2#

Available & Re-programmable

2FFF FFFF 2000 0000

Unused

CS1#

Available & Re-programmable

1FFF FFFF 1000 0000

J mode POM connector

CS0#

32-bit, multiplexed address/data bus

0FFF FFFF 0002 0000

Unused

_

Available

0001 FFFF 0000 0000

Synchronous burst SRAM 32Kx32

SRAMCS#

8-, 16-, or 32-bit access

PCI Express Interface

The PCI Express interface is a male card edge connector, based on the PCI Express Card Electromechanical (CEM) Specification, Revision 1.0a for an x1 interface. In addition to the PCI Express TX/RX pairs the card edge provides +12 VDC and +3.3 VDC, RefClk, and PERST#. The PCI Express TX/RX signals are laid out as 100-Ohm, controlled-impedance, microstrip-differential pairs. Trace length mismatch within signal pairs is not greater than 0.005". 3.4.1

RefClk

PCI Express RefClk enters the PEX 8311RDK through the PCI Express card edge (male) connector. RefClk is laid out as a 100-Ohm, controlled-impedance, microstrip-differential pair. Trace length mismatch is not greater than 0.005". Land is provided for the PCI Express RefClk to be generated onboard by an optional clock synthesizer (U12), using a 25-MHz crystal for the seed frequency. The PEX 8311RDK can use the IC557G-03 part from Integrated Circuit systems, Inc., though any comparable synthesizer is sufficient. RefClk is routed to the PEX 8311. An unused 100MHz reference clock (REFCLK2) is also available from (U12). RefClk routing is laid out as a 100-Ohm, controlled-impedance, microstrip-differential pair. Trace length mismatch within this pair is less than 0.005". When using the optional on board clock generator R12 and R13 should be removed to ensure that the locally generated clock is not driven to the PCI Express edge connector (P1). In addition, R1 and R2 should be populated to route the on board clock to the PEX 8311. The components for the on-board PCI Express clock circuitry are not assembled nor do they appear on the BOM. Customers who require this feature must source and assemble the components themselves. PLX takes no responsibility for boards damaged during this operation. 3.4.2

PERST#

PERST# is the fundamental Reset signal to the PEX 8311, from the PCI Express edge connector. 10

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

3.4.2.1

Reset Circuitry

The reset pushbutton (SW1) allows the user to force the PEX 8311 PERST# signal low. This causes a full reset of the device and the local bus logic. Pressing the reset button causes LRESET# to be asserted and will cause all EEPROM values to be re-loaded. Pressing the pushbutton reset will also clear all configuration registers including the PCI Express configuration registers. The PEX 8311 will have to be re-enumerated by the host before it will respond to PCI Express memory transactions. 3.5

LED Indicators

The PEX 8311RDK provides several LED indicators, including power-on indication and programmable PEX 8311 GPIO lane status indication. Table 3-4 provides a quick explanation of each LED indicators. By default GPIO[3:1] are configured as inputs and pulled high and GPIO0 shows the link status. By changing GPIOCTL[13:12] in the SPI EEPROM (U2) the GPIO lines can be reconfigured to reflect the lower four bits of the LTSSM state machine. See the PEX8311 data book for additional details. Table 3-4. PEX 8311RDK LED Indicators Indicator Type Board Power Indication

3.6

Location LED5 LED6 LED8

GPIO0

LED1

GPIO1 GPIO2 GPIO3

LED2 LED3 LED4

LED ON PCI Express 12V power on 3.3V power is on 2.5V power is on Output OFF (0) – Link Down ON (1) – Link Up ON, GPIO1 = Input by default ON, GPIO2 = Input by default ON, GPIO3 = Input by default

PEX 8311RDK Power

The PEX 8311RDK has two sources for DC power. The first source is the card edge connector (P1). This x1 connector provides up to 500 mA at +12VDC, and 3.0A at +3.3VDC. Card edge power is intended to power only PEX 8311RDK components. The second source, the ATX 4-pin connector (J4), provides +12VDC, and the +5VDC power supplied to the POM connector. The electronic devices on the RDK require +1.5V, +2.5V, and +3.3V DC power. A 5A LDO regulator (U4) is used to convert the PCI Express +12 VDC to +3.3 VDC, a 2.5A LDO regulator (U9) is used to convert the PCI Express +3.3 VDC to +2.5 VDC and a 250mA regulator (U3) is used to convert the PCI Express +3.3 VDC to +1.5 VDC power for the on board devices. As long as the output current from the voltage converter remains less than the maximum current outputs from the LDOs, the RDK board will function correctly. 3.6.1

PEX 8311 Bridge Device Power

The PEX 8311 bridge device power requires the following: ƒ ƒ ƒ

VDD Core +1.5 VDC ±10% +2.5 VDC ±10% VDD I/O +3.3 VDC ±10%

Care must be taken to ensure that the power sequencing requirements of the PEX 8311 are met – please refer to the PEX 8311 data book for further details. As shipped the absolute maximum current required for the PEX 8311RDK supplies is detailed in Table 3-5. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

11

Table 3-5. PEX 8311RDK Power supply currents Power Supply

Maximum required by the RDK

Maximum available from the Regulator

+1.5 VDC

240mA

250mA

+2.5 VDC

220mA

2.5A

+3.3 VDC

450mA

5A1

Note 1: A maximum of 1.8A is available when U4 is fed from the 12V supply of a 10W PCI Express connector.

When using the 1.5V supply to provide power to the uncommitted FPGA it may be necessary to change U3 to a larger regulator to ensure sufficient power supply current is available. 3.6.2

PEX 8311 Power Jumpers and Resistor options

Various power jumpers and resistor options are available on the PEX 8311 RDK to allow the power consumption of the PEX 8311 to be measured under different operating conditions. Table 3-6 details the jumper and resistor settings for the main power options. For the uncommitted FPGA power options please see section 4.4.2.4 Uncommitted FPGA power supplies. Table 3-6. PEX 8311RDK Power jumper and resistor options

12

Jumper

Factory Setting

Description

J7

CLOSED

+3.3V supply to PEX 8311

J8

CLOSED

+1.5V supply to PEX 8311

J9

CLOSED

+2.5V supply to PEX 8311

R21

ASSEMBLED

R22

NOT ASSEMBLED

R23

ASSEMBLED

R27

NOT ASSEMBLED

Link PCI Express 12V supply to U4 (+3.3V regulator) Link ATX (J4) 12V supply to U4 (+3.3V regulator) U4 (3.3V Regulator) provides +3.3V supply to RDK PCI Express 3.3V supply (P1) provides +3.3V supply to RDK

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

3.7

Power Management Signaling

Local devices assert the PMEIN# pin to signal a Power Management event. The PEX 8311 converts the PMEIN# signal to PCI Express Power Management Event (PME) messages. There are no internal events that cause a PME message to be sent upstream. When the PME message is sent to the host, the PWRMNGCSR register PME Status bit is set and a 100-ms timer is started. If the status bit is not cleared within 100 ms, another PME message is sent. When the upstream device is powering down the downstream devices, it first places all devices into the D3hot state. It then sends a PCI Express PME_Turn_Off message. After the PEX 8311 receives this message, it stops sending PME messages upstream. The PEX 8311 then sends a PME_TO_Ack message to the upstream device and places its link into the L2/L3 Ready state. The downstream device is now ready to be powered down. If the upstream device changes the PEX 8311 power state back to D0, PME messages are re-enabled. The PCI Express PME_Turn_Off message terminates at the PEX 8311, and is not communicated to the PCI devices. The PEX 8311 does not issue a PM_PME message on behalf of a downstream PCI device while its upstream link is in the L2/L3 non-communicating state. To avoid loss of PME# assertions in the conversion of the level-sensitive PMEIN# signal to the edgetriggered PCI Express PM_PME message, the PMEIN# signal is polled every 256 ms by the PEX 8311 and a PCI Express PM_PME message is generated if PME# is asserted. The PMEIN# signal is used only when the PEX 8311 is in Endpoint Mode. 3.7.1

Wakeup

The PEX 8311 asserts the WAKEOUT# signal or sends a PCI Express beacon for the following: ƒ

PMEIN# pin is asserted while link is in L2 state

ƒ

PCI Express beacon is received while link is in L2 state

ƒ

PCI Express PM_PME Message is received

A beacon is transmitted if the following are true: ƒ

PMEIN# pin is asserted while link is in L2 state

ƒ

DEVSPECCTL register Beacon Generate Enable bit is set

ƒ

PWRMNGCSR register PME Enable bit is set

The WAKEOUT# signal is used only when the PEX 8311 is in Endpoint mode. 3.8

Endpoint/Root Complex operation

The PEX 8311 RDK has been designed to demonstrate the operation of the PEX 8311 in Endpoint Mode. While the PEX 8311 RDK has not been designed for Root Complex mode operation it is possible to achieve limited Root Complex mode functionality. The following notes indicate how this may be achieved. PLX has not tested operation of the board in Root Complex mode so customers who require this feature do so at their own risk and must source and assemble the components themselves. PLX takes no responsibility for boards damaged during this operation To operate the PEX 8311 in Root Complex mode the PEX 8311 ROOT_COMPLEX# input should be pulled low by removing R6 and adding R7. In Root Complex mode the local bus of the PEX 8311 will be the upstream bus so some local intelligence will need to be added to act as the system host and enumerate any downstream device. Local intelligence may be added by attaching a suitable processor to either the POM (J3) connector, the test headers (LAH1-6) or by using the prototyping footprints. When operating in Root Complex mode the internal clock (CLKIN) of the PEX 8311 must be supplied by an external clock source. To use the clock source on the RDK remove R53 and assemble R52, R150, C96, C97 and U13. The maximum operating frequency for U13 should be 66MHz. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

13

As the PEX 8311 is now the upstream device it may be necessary for the PEX 8311 RDK to source the PCI Express clock. This can be achieved by populating the onboard PCI Express clock circuit – see sheet 7 of the schematics. To route the PCI Express clocks to the PEX 8311 remove R12 and R13 and insert R1 and R2. When operating in Endpoint mode the power for the PEX 8311RDK is normally provided by the PCI Express edge connector. If power is unavailable from this connector other means must be used to provide the +12V and +3.3V required by the board. It is possible to use the ATX connector (J4) to provide +12V to the 3.3V regulator U4 by removing R21 and populating R22 with a 0 ohm jumper. The PCIE3.3VCC can then be provided by U4 by populating R27 with a 0 ohm jumper. Extreme care must be taken to ensure that the power sequencing requirements of the PEX 8311 are still met when using the supplies in this manner. If there is any doubt with regards to power sequencing use one or more of J7, J8 and J9 to provide the supplies to the PEX 8311 from properly sequenced external sources. The PCI Express edge connector is obviously designed for use in Endpoint mode as an adapter card. A suitable converter will be required to allow other PCI Express devices/cards to be plugged into the RDK. In addition, it may be necessary to provide a downstream PCI Express clock. The spare REFCLK2 may be used for this function although care will be required with regards to the routing of this to the downstream device.

14

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

4.

Mechanical Architecture

Figure 4-1 illustrates the PEX 8311RDK and component placement.

Figure 4-1. PEX 8311RDK Component Placement The PEX 8311RDK’s form factor is based on the PCI Express CEM specification. The board is an eightlayer 6.6"L x 8.15"W PC board. The board height is greater than that noted in the PCI Express CEM specification and care must be taken to ensure that the board will fit within the target PC. It may be necessary to leave the case of the PC open or use an open chassis PC when using the PEX 8311 RDK. If this is the case then appropriate heath and safety measures should be taken when using the system in this manner. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

15

4.1

Monitoring Points, Test headers, Indicators, Control, and DIP Switch Summary

This section summarizes the interfaces available on the PEX 8311RDK for controlling and monitoring PEX 8311 performance. 4.1.1

Monitoring Points

ƒ

Six ground test points (TP3-8), are scattered across the PEX 8311RDK to provide probe reference points

ƒ

Voltages to the PEX 8311 can be monitored at the following locations: ƒ

J8 (1.5 VCC)

ƒ

J9 (2.5 VCC)

ƒ

J7 (3.3 VCC)

ƒ

Three 3.3 VCC test points (TP9-11), are scattered across the PEX 8311RDK to allow voltage monitoring.

ƒ

TP1 is connected to the PEX 8311 PWR_OK output

ƒ

TP2 can be used to monitor the PEX8311 internal clock

ƒ

External power can be monitored at the ATX connector (J4)

ƒ

J1 provides access to the PEX 8311 JTAG port; TCK, TDI, TDO, and TMS

ƒ

LAH 1-6 Logic analyzer test headers to connect to monitor local bus activity, see Section 4.1.2.1 Test Headers

4.1.2

Headers

4.1.2.1

Test Headers

The RDK board has six (6) 0.1”, 2x10 logic analyzer headers (LAH1-6) that follow the HP format and can be used for probing or prototype area extension. All PEX 8311 Local Bus signals, configuration and status signals are well arranged within these headers. Headers LAH2 and LAH3 contain Local Bus address signals. Headers LAH4 to LAH6 contain Local Bus data signals. Headers LAH1 and LAH5 contain Local Bus control and status signals. These headers do not provide any power source. Schematic page 5 provides the connector signal details. 4.1.2.2

JTAG Headers

There are two independent JTAG test ports on the PEX 8311 RDK. J1 is a 0.1”, 6 x 1 header which allows access to the PEX 8311 JTAG interface. This can be used to check connectivity of the device and to allow customers to develop their own test programs. With the exception of BSDL models PLX does not provide any additional boundary scan test software for the PEX 8311 or the PEX 8311 RDK. J2 is a 0.1” 9 x 1 header which is connected directly to the Xilinx CPLD (U10). This header allows the CPLD to be re-programmed by the user at any time. PLX does not provide the programming software or the lead to allow re-programming of the CPLD. By reprogramming the CPLD the user can change the functionality of the board. However, customers who re-program the CPLD do so at their own risk. PLX takes no responsibility for boards damaged or rendered inoperable while re-programming the CPLD.

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PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

4.1.3

Indicators

By default GPIO[3:1] are configured as inputs and pulled high. GPIO0 (and LED0) shows the link status. By changing GPIOCTL[13:12] in the SPI EEPROM (U2) the GPIO[3:0] lines and LED[3:0] can be reconfigured to reflect the lower four bits of the LTSSM state machine. See the PEX8311 data book for additional details. The other LED’s on the PEX 8311 indicate operation of the power supplies as detailed in Table 3-4. PEX 8311RDK LED Indicators 4.1.4

Controls Table 4-1. PEX 8311RDK Default Jumper Settings

Jumper

Factory Setting

JP1

OPEN

Pull down BAR0ENB# when closed

JP2

OPEN

GPIO0 drives LED1

JP3

1-2

Pull GPIO1 high

JP4

1-2

Pull GPIO2 high

JP5

1-2

Pull GPIO3 high

J7

CLOSED

+3.3V supply to PEX 8311

J8

CLOSED

+1.5V supply to PEX 8311

J9

CLOSED

+2.5V supply to PEX 8311

4.2 4.2.1

Description

PEX 8311RDK Layout Information Trace Routing Design Rules

The characteristic trace impedances are within the PCI Express specification (100 Ohm ±5%) for the differential, and within the PCI specification (55 Ohm ±10%) for the single-ended. 4.2.2

Power Decoupling

Power decoupling is provided by two means – plane capacitance (provided by the PCB stackup) and discrete decoupling capacitors. Plane capacitance filters noise above approximately 100 MHz. The footprints for the discrete decoupling capacitors are designed such that the inductance between the pad and plane is reduced by careful via placement. (Refer to Figure 4-2. PEX 8311RDK Decoupling Capacitor Footprints)

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

17

Figure 4-2. PEX 8311RDK Decoupling Capacitor Footprints 4.2.3

PCB Stackup

The PEX 8311RDK is an 8-layer, 60-mil thick PCB. The target signal impedance for all routing layers is 55 Ohms ±10% single-ended impedance and 100 Ohms ±5% differential. Figure 4-3 details the layers used in the PCB manufactuer. The thickness of the various layers is detailed in Table 4-2. Layer thickness. SOLDERMASK L1, SIGNAL 1 Controlled Impedance

PREPEG L2, GROUND

Controlled Impedance

LAMINATE L3, SIGNAL 2 PREPEG L4, POWER LAMINATE L5, POWER PREPEG L6, SIGNAL 3

Controlled Impedance

LAMINATE L7, GROUND

Controlled Impedance

PREPEG L8, SIGNAL 4 SOLDERMASK

Figure 4-3. PEX 8311RDK Stackup 18

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

Table 4-2. Layer thickness Layer L1

Type Prepeg

L2 Core L3 Prepeg L4 Core L5 Prepeg L6 Core L7 Prepeg L8

4.3

Thickness (mils) 0.60 4.00 1.20 5.00 1.20 10.00 2.60 10.00 2.60 10.00 1.20 5.00 1.20 4.00 0.60

MidBus LAI Footprints

The PEX 8311RDK has one half-size MidBus LAI footprint site (J5), which can be used to probe the highspeed PCI Express serial lanes, or populated with a shroud to allow third-party PCI Express logic analyzers to view the serial data. The board is not shipped with the shroud assembled nor does the shroud appear on the BOM. Customers who require this feature must source and assemble the shroud themselves. PLX takes no responsibility for boards damaged during this operation. 4.4 Prototyping Area The RDK board contains a small prototyping area with various surface-mount footprints and a 20 x 10 0.1” pitch through-hole grid. 4.4.1 Surface Mount Footprints The prototyping area of the PEX 8311 RDK has six (6) surface mount footprints; see Table 4-3 for details. These footprints can accommodate a variety of devices. Although FP2 is deigned to accommodate FPGA’s other devices may be assembled on this footprint.

Table 4-3. Six (6) Surface Mount Footprints Package

Qty

Pin Pitch

Schematic Reference

SOT-223

1

0.1”

U14

Voltage Regulator

20-pin SSOP

1

0.05"

FP1

Discrete Logic, Configuration Memory

28-pin SOIC

1

0.05"

FP3

Discrete Logic

48-pin SSOP

2

0.025"

FP4, FP5

144-pin PQFP

1

0.5mm

FP2

Example Applications

Discrete Logic, data transceivers FPGA’s, CPLDs, TI C542/KC542/LC548/ LC549/VC549, SH7604, IDT RC32364

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

19

4.4.2 Uncommitted FPGA footprint The footprint FP2 has been designed to accept either a 100 pin Altera Cyclone FPGA such as the EP1C3T144 or a 100 pin Xilinx Spartan-3E FPGA. Although care has been taken to ensure that the configurable resistor options and connections comply with these devices it is recommended that the user carefully checks the latest documentation from the FPGA manufacturer in case of product changes subsequent to the publication of this document. In addition to the devices noted above other parts may also be assembled onto FP2. However, it is up to the user to determine the appropriate connections between the device and the PEX 8311 local bus. It should be noted that PLX does not provide FPGA code examples. Section 7 - CPLD Verilog Code – details the code which is used in the on board CPLD and this may be used as a guide. 4.4.2.1 Uncommitted FPGA connections The following modules can be used in conjunction with the uncommitted FPGA footprint: • • • • •

Unpopulated configuration Resistors Configuration PROM JTAG headers User VCC Through hole pads

Depending on the application one or more of these can be used to interconnect the FPGA to the existing circuitry on the PEX 8311 RDK, to set up FPGA configuration and/or to link to other uncommitted elements on the FPGA 4.4.2.2 Uncommitted FPGA to PEX 8311 local bus The uncommitted FPGA can be connected to the PEX 8311 local bus in two ways: a) Using the resistor options b) Wiring between the through hole pads (PF1 to PF144) and the test headers (LAH1 to LAH6) Any combination of the above can be used. Table 4-4 shows the resistor options used to connect the Altera Cyclone or the Xilinx Spartan-3E arrays to the PEX 8311 local bus.

20

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

Table 4-4. Uncommitted FPGA resistor configuration FPGA Xilinx Pin Altera Pin Pin No. Name Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

PROG_B I/O I/O I/O I/O IP I/O I/O 1.2V IP GND IP 3.3V I/O I/O I/O I/O IP GND I/O I/O I/O I/O IP I/O I/O GND 3.3V IP 2.5V I/O I/O I/O I/O I/O IP GND IP I/O INIT_B IP 3.3V I/O I/O 1.2V GND IP IP 3.3V I/O

Local Signal

INIT_DONENote 1 I/O LD0 I/O LD1 I/O LD2 I/O LD3 I/O LBG1 I/O LD4 3.3V LA2_X GND I/O BREQo I/O LA2_A I/O (nCS0) LA20 DATA0 USERo nCONFIG GPIO0 1.5V LA4_X CLK0 LCLK_T CLK1 LA5_X GND GND nCEO USERi nCE LA6_X MSEL0 LA7_X MSEL1 LA8_X DCLK GPIO1 I/O LD5 I/O LD6 I/O LA4_A I/O LA5_A 3.3V LA21_X GND I/O LD7 I/O LD8 I/O LD9 I/O LD10 I/O LD11 I/O LINTo# I/O LA6_A I/O LSERR# I/O LD12 I/O Note 1 I/O CS_3# I/O LA7_A GND LA9_X 3.3V LA10_X GND 1.5V I/O LA16 I/O LA17 I/O LA8_A I/O LD15

Bus No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14

Xilinx link Xilinx Xilinx Altera link Altera Altera resistor Voltage R Capacitor resistor Voltage R Capacitor 180 182 186 191 196 198 200 203 209 214 220 225 231 User IO 237 User IO 244 User IP 178 User IO 183 187 192 User IP 199 202 207 212 216 224 228 233 236 240 242 246 278 282 287 292 294 300 305 312 320 323 328 333 327 338

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190

103

262 201

104

235

265 267

112

256

107

275

281

311 380

115

116

117

User IO 182 186 191 196 198 200 176 209 214 219 225 Note 2 234 239 241 NC 249 178 Note 2 Note 2 Note 2 Note 2 Note 2 199 202 205 211 218 223 228 233 236 240 242 246 277 282 287 User IO 294 298 307 313 320 323 328 333 336 338

102 195

210

104

235 235

251 272

291 354 318 374

107

123 124

21

FPGA Xilinx Pin Altera Pin Local Signal Pin No. Name Name 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

22

I/O I/O I/O I/O GND IP IP I/O I/O I/O GND I/O DIN 3.3V 2.5V I/O I/O I/O IP I/O CCLK DONE GND I/O I/O I/O I/O IP 3.3V 1.2V I/O I/O I/O IP I/O I/O I/O I/O IP GND I/O I/O I/O I/O IP I/O I/O I/O GND 3.3V

Bus No.

I/O LD16 B15 I/O LD17 B16 I/O LD18 B17 I/O LD19 B18 I/O LA9_A B19 I/O LA18 B20 I/O LA19 B21 I/O LD22 B22 I/O LD23 B23 I/O LD24 B24 I/O LA10_A B25 I/O LD25 B26 GND Note 1 B27 1.5V B28 GND B29 3.3V LA11_X B30 I/O LD26 B31 I/O LD27 B32 I/O DACK0# B33 I/O LD28 B34 I/O Note 1 B35 I/O Note 1 B36 I/O LA11_A C1 I/O LD29 C2 I/O LD30 C3 I/O LD31 C4 I/O ADS# C5 I/O DACK1# C6 I/O LA12_A C7 GND C8 3.3V LA15_X C9 I/O BIGEND# C10 I/O BLAST# C11 I/O LA31/DT/R# C12 I/O LA29/ALE C13 CONF_DOGPIO2 C14 nSTATUS GPIO3 C15 TCK F_TCK C16 TMS F_TMS C17 TDO F_TDO C18 I/O BREQi C19 CLK3 LA12_X C20 CLK2 PMEIN#_X C21 I/O BTERM# C22 TDI F_TDI C23 I/O CCS# C24 I/O DMPAF/EOT C25 I/O DREQ0# C26 I/O LA13_A C27 I/O LA14_A C28

Xilinx link Xilinx Xilinx Altera link Altera Altera resistor Voltage R Capacitor resistor Voltage R Capacitor 340 343 346 349 344 279 283 289 293 295 303 308 315 321 326 329 334 337 339 342 345 347 387 391 394 397 400 403 407 410 416 422 427 430 433 User IO User IO User IO User IP 452 385 388 393 396 User IP 402 404 409 415 420

366

368 357

126 121

384

392 471

129 136

455

474 480

139

340 343 346 349 276 279 283 289 293 295 301 308 317 321 326 330 334 337 339 342 User IO User IO 386 391 394 397 400 403 405 411 417 422 427 430 433 Note 2 Note 2 442 445 450 385 NC NC 396 399 402 404 409 413 419

366 376 363 369

401 408

126 127

130

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FPGA Xilinx Pin Altera Pin Pin No. Name Name 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

IP 2.5V I/O I/O I/O I/O IP TMS TDO TCK IP I/O I/O IP 1.2V I/O I/O GND IP IP 3.3V I/O I/O I/O I/O I/O GND GCLK8 IP I/O I/O I/O GND I/O I/O IP 2.5V 3.3V I/O I/O IP I/O I/O TDI

GND 3.3V I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 3.3V GND 1.5V GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 1.5V GND 3.3V GND I/O I/O I/O I/O I/O I/O

Local Signal LA22_X DP0 DP1 DP2 DP3 LA30/DEN# LA3_A LA15_A LA21_A LA23 DREQ1# LBR1 LA24 LA13_X LA14_X LA25 LA26 LA22_A LD13 LINTi# LRESET# LBE0# LBE1# LCLK_T LW/R# LD14 READY# LA28_A WAIT# LA3_X LA28_X

LD20 LD21 LA27 LBE2# LBE3# PMEIN#_A

Bus No. C29 C30 C31 C32 C33 C34 C35 C36 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36

Xilinx link Xilinx Xilinx Altera link Altera Altera resistor Voltage R Capacitor resistor Voltage R Capacitor 424 429 432 435 438 441 444 172 171 170 502 507 510 513 520 523 530 538 542 548 562 558 563 568 573 578 594 496 User IP 505 508 511 518 521 526 533 540 545 551 555 559 564 569 173

463

134

509

142

547

144

615

585 603

146 153

426 428 432 435 438 441 444 449 493 497 502 507 510 513 520 524 532 537 542 548 554 558 563 568 573 578 User IO User IO User IO 505 508 511 516 521 528 534 540 545 551 555 559 564 569 574

475 481

501 598 536 620

605 621 580 618

140

142 143

150 146

Notes: 1) The resistors used for the Xilinx programming pins will depend on the programming method used. Refer to Table 4-6, Table 4-8 and Table 4-9 for further details. 2) The resistors used for the Altera programming pins will depend on the programming method used. Refer to Table 4-5, Table 4-7 for further details. With the exception of the resistors noted in Table 4-5, Table 4-6, Table 4-7, Table 4-8 and Table 4-9 the resistor value will normally be 0 ohms. Depending on the I/O of the FPGA some additional signal noise may be seen. If this is the case then the value of the resistors used to link to the local bus signals may be increased to form a series termination resistor. The value required will depend on the loading but will typically be in the range of 30 to 100 ohms. PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

23

The power supplies for the FPGA’s normally require 2 resistors to be populated. One resistor is used to link the FPGA to a Vx bus (see the “…Link Resistor” column) and the second resistor is used to select the appropriate voltage (see the “…voltage R” column. In addition to the resistors it is recommended that the appropriate decoupling capacitor noted in the “…Capacitor” column is also assembled. The value required will be FPGA specific but is typically 10nF. 4.4.2.3 Programming the uncommitted FPGA There are three methods of programming or configuring the uncommitted FPGA: a) Program through the JTAG interface b) Program using the PEX 8311 GPIO c) Program using the Configuration PROM Of the above options (a) and (b) are available for both the Altera and Xilinx devices. Option (c) is only available for the Xilinx device. 4.4.2.3.1 Programming the FPGA through the JTAG interface Table 4-5 shows the resistor options and jumpers used to connect the 0.1”, 1 x 10 header JP6 to an Altera Cyclone array. JP6 can be used with programmers from Altera such as the ByteBlaster II, MasterBlaster etc. Depending on the programmer used pins 4 and 10 of JP6 may need to be pulled to the appropriate voltage, see notes 1 and 2 below and the appropriate Altera documentation.

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PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

Table 4-5. Altera Uncommitted FPGA JTAG interconnections FPGA JTAG program option

Altera FPGA using ByteBlaster II, MasterBlaster or ByteBlas 10 pin header.

Connector [pin]

JTAG signal

Link Resistor (value)

FPGA signal [pin]

Pull-up resistor or jumper

Pull-down resistor or jumper

JP6 [1]

F_TCK

R442 (0)

TCK [88]

-

R637 (10K)

JP6 [2]

GND

-

-

-

-

JP6 [3]

F_TDO

R450 (0)

TDO [90]

-

-

JP6 [4]

VCC1

-

-

-

-

JP6 [5]

F_TMS

R445 (0)

TMS [89]

R631 (10K)

-

JP6 [6]

VIO (3.3V)

-

-

-

-

JP6 [7]

NC

-

-

-

-

JP6 [8]

NC

-

-

-

-

JP6 [9]

F_TDI

R399 (0)

TDI [95]

R630 (10K)

-

JP6 [10]

NC2

-

-

-

-

-

-

R185 (0)

nCE [21]

-

R250 (0)

-

-

R439 (0)

nSTATUS [87]3

-

-

R436 (0)

CONF_DONE [86]4

-

-

R234 (0)

nCONFIG [14]5,6

-

-

R189 (0)

MSEL0 [22] 5

-

R250 (0)

-

-

R194 (0)

MSEL1 [23] 5

-

R250 (0)

5

-

R266 (0)

5,7

-

JP3 [2-3]

-

-

R230 (0)

DATA0 [13]

-

-

R197 (0)

DCLK [24]

JP5 [1-2] or JP5 NC + R117 (10K) JP4 [1-2] or JP4 NC + R116 (10K) JP2 [1-2] or JP2 NC + R114 (10K)

-

Notes: 1) This pin is connected to TP20. Connect this pin to the same supply voltage as the download cable. 2) For some programmers it may be necessary to tie this pin to GND. 3) nSTATUS is connected to GPIO3. During configuration ensure that GPIO3 is an input. This is the default condition for GPIO3. 4) CONF_DONE is connected to GPIO2. During configuration ensure that GPIO2 is an input. This is the default condition for GPIO2. 5) The connections for these pins assume only JTAG configuration is being used. When supporting non-JTAG configuration schemes see section 4.4.2.3.2. 6) nCONFIG is connected to GPIO0. The low to high transition begins configuration. If GPIO0 is programmed to be an output configuration can be enabled using this signal. 7) DCLK is connected to GPIO1. When JP3 is in position 2-3 GPIO1 is strapped to GND and must always be configured as an input. In addition to the above resistors the appropriate power supply and ground resistors must also be populated.

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

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Table 4-6 shows the resistor options and jumpers used to connect the 14 pin Target Interface connector (e.g. Molex part no. 87831-1420) JP7 to an Xilinx Spartan-3E array. JP7 can be used with appropriate programmers from Xilinx to configure the device using the JTAG interface. Table 4-6 also assumes that JP7 is connected directly to the Xilinx FPGA. It is also possible to create a scan chain with the configuration PROM (FP1) if used. This is detailed further in section 4.4.2.3.3. Depending upon the device, care should be taken with HSWAP_EN (pin 143). This pin configures the internal pull-up resistors. By default pin 143 will be connected to LBE3# (via R569) and is pulled high using RN2. This will disable the internal pull-ups. If the internal pull-ups are required this pin needs to be pulled low using R571 and R597. Table 4-6. Xilinx Uncommitted FPGA JTAG interconnections FPGA JTAG program option

Xilinx Spartan-3E array using 14 pin Target Interface Connector

Connector [pin]

JTAG signal

Link Resistor (value)

FPGA signal [pin]

Pull-up resistor or jumper

Pull-down resistor or jumper

JP7 [2]

Vref (2.5V)

-

-

-

-

1

TMS[108]

-

-

TCK [110]

-

-

TDO [109]

-

-

JP7 [4]

F_TMS

R172 (100Ω)

JP7 [6]

F_TCK

R170 (100Ω) 1 1

JP7 [8]

F_TDO

R171 (0)

JP7 [10]

F_TDI

R173 (100Ω) 1

TDI [144]

-

-

JP7 [12,14]

NC

-

-

-

-

JP7 [1,3,5,7,9, 11,13]

GND

-

-

-

-

-

-

R180 (0 or 56 Ω) 1,2

PROG_B [1]

JP5 [1-2] or JP5 NC

-

-

-

R348 (0)

DONE [72]

R358 (330 Ω) 3

-

-

-

R292 (0)

INIT_B [40]

JP4 [1-2] or JP4 NC + R116 4 (4K7)

R250 (0)

-

-

R309 (0)

M0 [62]

R368 (10K)

-

-

-

R297 (0)

M1 [60]

-

R361 (10K)

-

R367 (10k)

-

-

R284 (0)

M2 [57]

5

Notes: 1) The value of the series current limiting resistor may vary depending on the programmer and the programming voltage used. If using 3.3V programming then 56Ω is typically used. Refer to the appropriate Xilinx application notes for further information. 2) PROG_B is connected to GPIO3. GPIO3 is an input by default. 3) The resistor options shown pull DONE to 3.3V. Depending on the programming option selected DONE can be pulled to 2.5V using R358. 4) INIT_B is connected to GPIO2. GPIO2 is an input by default. 5) If this pin is connected to LA19 through R283 then R284 and R367 are not required as this pin is pulled high using RN11. In addition to the above resistors the appropriate power supply and ground resistors must also be populated.

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PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

4.4.2.3.2Programming the FPGA through the GPIO Table 4-7 shows the resistor options and jumper configurations required to interface the Altera cyclone FPGA programming pins to the PEX 8311 GPIO pins. The FPGA may then be configured by sending appropriate commands and data through the PEX 8311 GPIO to the FPGA programming pins. It should be noted that PLX does not provide software to program the FPGA. The SDK shipped with the PEX 8311 RDK provides .api calls to allow access to and changing of the GPIO pins. It is up to the user to develop software to program the FPGA used in their design. Table 4-7 assumes that programming of the Altera FPGA uses the Passive Serial Configuration method. Table 4-7. Programming the Altera Uncommitted FPGA through the GPIO PEX 8311 signal

Link Resistor (value)

FPGA signal [pin]

Pull-up resistor or jumper

USERo GPIO0 GND VCC GND GPIO1 GPIO2 GPIO3

R229 (0) R234 (0) R185 (0) R188 (0) R194 (0) R197 (0) R436 (0) R439 (0)

DATA0 [13] nCONFIG [14] nCE [21] MSEL0 [22] 2 MSEL1 [23] DCLK [24] CONF_DONE [86] nSTATUS [87]

JP2 NC + R1141 R254 (0) JP3 NC3 JP4 NC + R116 (10K) JP5 NC + R117 (10K)

Pull-down resistor or jumper R250 (0) R250 (0) -

Notes: 1) Depending on the device used, the pull-up R114 may not be required. GPIO0 should be configured to be an output. 2) For some devices MSEL0 should be pulled to ground. If this is required remove R254 and add R264 3) GPIO1 must be configured to be an output. In addition to the above resistors the appropriate power supply and ground resistors must also be populated. Table 4-8 shows the resistor options and jumper configurations required to interface the Xilinx Spartan-3E FPGA programming pins to the PEX 8311 GPIO pins. The FPGA may then be configured by sending appropriate commands and data through the PEX 8311 GPIO to the FPGA programming pins. It should be noted that PLX does not provide software to program the FPGA. The SDK shipped with the PEX 8311 RDK provides .api calls to allow access to and changing of the GPIO pins. It is up to the user to develop software to program the FPGA used in their design. Table 4-8 assumes that programming of the Xilinx FPGA uses the Slave Serial Configuration method. Depending upon the device, care should be taken with HSWAP_EN (pin 143). This pin configures the internal pull-up resistors. By default pin 143 will be connected to LBE3# (via R569) and is pulled high using RN2. This will disable the internal pull-ups. If the internal pull-ups are required this pin needs to be pulled low using R571 and R597. If HSWAP_EN needs to be pulled low and LBE3# is required then connect R571 (0) and R597(4K7) and lift pin 4 or pin 5 of RN2. Depending on the device and power supplies used it may be necessary to add a resistor from the 2.5V rail to ground to manage reverse current. Typically this resistor would be 118Ω or 110Ω and would only be required if the 2.5V supply for the FPGA was sourced from the USRVCC – see the Xilinx application notes for further details regarding reverse currents.

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

27

Table 4-8. Programming the Xilinx Uncommitted FPGA through the GPIO PEX 8311 signal

Link Resistor (value)

FPGA signal [pin]

Pull-up resistor or jumper

Pull-down resistor or jumper

GPIO3

R180 (56 Ω)

PROG_B [1]

JP5 NC

-

USERi

R347 (0)

DONE [72]

GPIO2

R292 (0)

INIT_B [40]

VCC

R309 (0)

M0 [62]

R368 (10K)

-

VCC

R297 (0)

M1 [60]

R350 (10K)

-

R367 (10K)

-

2

R348 (0) + 1 R358 (330 Ω) JP4 NC + R116 (4K7)

-

VCC

R284 (0)

M2 [57]

GPIO1

R315 (0)

DIN [63]

JP3 NC

-

GPIO0

R345 (56 Ω)

CCLK [71]

JP2 NC

-

Notes: 1) R348 and R353 are only required if BitGen option DriveDONE = No – see the appropriate Xilinx data sheet for more details. Ideally pin 3 or pin 6 of RN10 should be lifted if R348 and R353 are used. 2) If LA19 is connected to this pin through R283 then R284 and R367 are not required as this pin is pulled high using RN11. In addition to the above resistors the appropriate power supply and ground resistors must also be populated. 4.4.2.3.3 Programming the uncommitted FPGA from the configuration PROM Xilinx FPGA’s can be configured using Platform Flash In-System Programmable Configuration PROMs. FP1 is designed to accept the VO20/VOG20 packaged versions of the XCFxxS platform flash PROMs. Table 4-9 details the resistor configurations required to interface a platform flash assembled on FP1 to a Xilinx Spartan-3E array assembled on FP2. It also details the resistor options for connecting the platform flash JTAG interface to JP7 to allow the platform flash to be programmed using the JTAG interface. JP7 is the 14 pin Target Interface connector (e.g. Molex part no. 87831-1420) and can be used with appropriate programmers from Xilinx to configure the device using the JTAG interface. The programming method detailed in Table 4-9 is master serial mode. Other programming modes may also be selected using the appropriate resistor options. The JTAG TDO output from the platform flash is routed to the TDI input of the Xilinx FPGA. If the JTAG interface is not required the resistors marked with a † in Table 4-9 may be removed. Depending on the device and power supplies used it may be necessary to add a resistor from the 2.5V rail to ground to manage reverse current. Typically this resistor would be 118Ω or 110Ω and would only be required if the 2.5V supply for the FPGA was sourced from the USRVCC – see the Xilinx application notes for further details regarding reverse currents.

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PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

Table 4-9. Platform Flash to Xilinx interconnect Connector [pin]

JTAG Signal

Plaftorm Flash Signal [pin]

JP7 [2] JP7 [4] JP7 [6] JP7 [8] JP7 [10] JP7 [12,14] JP7 [1,3,5,7,9, 11,13] -

Vref (2.5V) F_TMS F_TCK F_TDO F_TDI NC

TMS [5] TCK [6] TDI [4] -

R164 (0) R165 (0) † R171 (0) R163 (0) -

TDO [109] -

-

Pull-down resistor or jumper -

GND

-

-

-

-

-

-

D0 [1] CLK [3]

R161 (0) R162 (0)

DIN [63] CCLK [71]

-

-

-

CF# [7]

R166 (0)

PROG_B [1]

-

-

OE/RESET# [8]

R167 (0)

INIT_B [40]

-

-

CE# [10]

R169 (0)

DONE [72]

JP7 [6] JP7 [4]

F_TCK F_TMS

GND [11] TDO [17] VCCINT [18] VCCO [19] VCCJ [20] TCK [6] TMS [5]

R168 (0) †,5 R159 (56 Ω) R157 (0) R154 (0) 4 R151(0) 4 † R170 (56 Ω) † R172 (56 Ω) R309 (0) R297 (0) R284 (0)

TDI [144] TCK [110] TMS[108] M0 [62] M1 [60] M2 [57]

JP5 NC + R180 1 (0) +R117 (4K7) JP4 NC + R292 2 (0) +R116 (4K7) R348 (0) + R358 3 (330 Ω) -

Link Resistor FPGA signal (value) [pin]

Pull-up resistor or jumper

-

-

-

R379 (10K) R361 (10K) R375 (10K)

Notes: 1) If GPIO3 is to be used JP5 can be connected to position [1-2]. Care must be taken to avoid accidentally placing the FPGA into programming mode or resetting the device. 2) If GPIO2 is to be used JP4 can be connected to position [1-2]. Care must be taken to avoid accidentally placing the FPGA into programming mode or resetting the device. 3) R348 and R353 are only required if BitGen option DriveDONE = No – see the appropriate Xilinx data sheet for more details. Ideally pin 3 or pin 6 of RN10 should be lifted if R348 and R353 are used. 4) R154 and R151 are used when 3.3V programming is required. Other programming voltages are possible but will require pull’s on the Xilinx array to be modified appropriately. See the Xilinx data sheets for further details. 5) If the Xilinx FPGA is not linked to the scan chain then remove R159 and add R158 (0). This will link the TDO of the Platform Flash to the JTAG connector TDO pin (F_TDO). As noted above, in Table 4-9 the JTAG TDO output from the platform flash is routed to the TDI input of the Xilinx FPGA i.e. the Program Flash is the first device in the chain. The scan chain can also be configured so that Xilinx device is the first device in the chain by removing R159, R163 and R171 and populating R158 (0), R160 (0) and R173 (56 Ω). 4.4.2.4 Uncommitted FPGA power supplies The device mounted onto FP2 may require a voltage level not provided by the voltage regulators assembled on the RDK. To accommodate this, the uncommitted USRVCC circuit can be populated with an appropriate voltage regulator. Although the schematics show U14 to be a 2.5V regulator any comparable regulator which can fit the SOT-223 layout can be used.

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

29

The uncommitted regulator can be fed from either the PCIE3.3VCC rail (populate R175) or from the 5V supply provided by the ATX connector J4 (populate R174). The uncommitted USRVCC could also be used to provide an additional 1.5VCC as there is relatively little spare current available from U3. It should be noted that not all power rails are available for all the Vx bus resistor options associated with FP2 and it may be necessary to wire directly from the regulator to the appropriate PFx hole under some circumstances. 4.4.2.5 Uncommitted FPGA Pull-ups/downs Many of the pins associated with the uncommitted FPGA footprint can be pulled high or low. These pulls are set up using the appropriate resistor to link to a Vx bus and then selecting the voltage the pin should be pulled to using a second resistor. FPGA pins which are connected to LA or control pins of the PEX 8311 will not normally require additional pulls as these are already pulled to the correct value – see sheet 3 of the schematics. 4.4.2.6 Increasing the number of unused uncommitted FPGA I/O The vast majority of the I/O of the FPGA’s are used in connecting to the PEX 8311. The settings detailed in section 4.4.2.2 show the FPGA connected to the PEX 8311 in C mode using a 32 bit data bus. In addition every feature of the PEX 8311 is connected to the FPGA. For some applications more FPGA I/O will be required for user circuitry attached to the FPGA. There are several ways in which additional I/O can be released: 1) C mode of J mode When operating in C mode both the address and data buses have to be routed to the FPGA. If the board is re-configured to operate in J mode (see section 5) those signals which were previously allocated to the LA bus are no longer required and can be used as additional I/O. 2) Data bus width The data bus is currently configured to be a 32 bit bus. The LBRDx registers can be reconfigured to allow operation in 8 or 16 bit mode, thereby releasing the I/O which are connected to the unused data lines. It may be useful to only change LDRD1 to a different bus width. This will allow 32 bit accesses to the SBSRAM using local address space 0. It should be noted that if the FPGA is to access any of the PEX 8311 registers that access must be a 32 bit wide access so reducing the bus width is really only a solution for slave designs. 3) Bus Mastering or Slave only designs If the FPGA is only going to be used as a slave device then it may not be necessary to link all of the local bus control signals to the FPGA. 4) Address bus subset CS3# is routed to the FPGA and can be used as a chip select for the device. If only a small number of addresses are going to be decoded by the FPGA the upper portion of the LA bus can be left unconnected releasing FPGA I/O.

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PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

5.

RDK Mode Configuration

The RDK hardware’s Processor/Local Bus is pre-configured for non-multiplexed data and address (C Mode) Processor/Local Bus operation. It can be reconfigured for multiplexed data and address Processor/Local Bus operation (J Mode). Several resistors configure the RDK hardware’s Processor/Local Bus for C or J Mode. The specific resistors to install and remove for each mode are detailed in Table 5-1. (‘X’ means installed; no ‘X’ means removed.) Table 5-1. RDK Board Mode Configuration Resistors

Value

C Mode (Default)

J Mode

Mode Pins Configuration R32

1/10w, 10K ohm, 5%

R33

1/10w, 10K ohm, 5%

X

R34

1/10w, 0 ohm, 5%

X

R35

1/10w, 0 ohm, 5%

X

X

Data/Address Pins Configuration R74

1/10w, 0 ohm, 5%

X

R75

1/10w, 0 ohm, 5%

R76

1/10w, 0 ohm, 5%

R77

1/10w, 0 ohm, 5%

R84

1/10w, 0 ohm, 5%

R85

1/10w, 0 ohm, 5%

X

R87

1/10w, 0 ohm, 5%

X

R88

1/10w, 0 ohm, 5%

R93

1/10w, 0 ohm, 5%

R94

1/10w, 0 ohm, 5%

R95

1/10w, 0 ohm, 5%

R96

1/10w, 0 ohm, 5%

X X X X

X X X X X

R97

1/10w, 0 ohm, 5%

R100

1/10w, 0 ohm, 5%

R103

1/10w, 0 ohm, 5%

R106

1/10w, 0 ohm, 5%

R108

1/10w, 0 ohm, 5%

R109

1/10w, 0 ohm, 5%

R110

1/10w, 0 ohm, 5%

R111

1/10w, 0 ohm, 5%

R112

1/10w, 0 ohm, 5%

R113

1/10w, 0 ohm, 5%

X

R50

1/10w, 10K, 5%

X

R51

1/10w, 4.7K ohm, 5%

X X X X X X X X X

LA29/ALE

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

X

31

6.

Examples of Testing the OnBoard 32Kx32 SBSRAM with PLXMon

1) Single read/write from/to on board SBSRAM a) At the lower command line window of PLXMon, type in the following commands to perform single 32bit, 16bit and 8bit memory read/write transfers from/to the on board SBSRAM. dl s0 1 <= read one 32-bit long word from address s0 el s0 88888888 <= write 32-bit data, 88888888h, to address s0 dw s0 1 <= read one 16-bit word from address s0 ew s0 8888 <= write 16-bit data, 8888h, to address s0 db s0 1 <= read a byte from address s0 eb s0 88 <= write 8-bit data, 88h, to address s0 2) DMA burst read/write from/to on board SBSRAM: a) At the lower pane of the PLXMon, type Vars to obtain the addresses for HBuf, 60K-byte DMA scratch buffer located in the PC’s main memory. For example, assume the HBuf has physical address starting at 01F80000h. b) Enter 8 long words of test data to the SBSRAM. For example, el s0 11111111 el s0+4 22222222 el s0+8 33333333 el s0+c 44444444 el s0+10 55555555 el s0+14 66666666 el s0+18 77777777 el s0+1c 88888888 c) Click the DMA button on PLXMon to open the DMA registers window. d) Configure DMA CH0 for burst transfer and the transfer direction is from Local-to-PCI. The settings on DMA channel 0 would be similar to the following Mode (80h): 143 PCI address (84h): 01F80000 Local address (88h):00000000 Transfer size (8ch): 100 Descriptor pointer (90h):8 Check the box for data transfer enable e) Click on the [Start Transfer] button to transfer data from on Board SBSRAM to DMA scratch buffer. f)

Compare the data from step ‘b’ by typing the dl HBuf commend.

g) Change the contents of the DMA scratch buffer el HBuf 99999999 el HBuf+488888888 el HBuf+877777777 el HBuf+c66666666 el HBuf+10 55555555 el HBuf+14 44444444 el HBuf +18 33333333 el HBuf+1c22222222 PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

33

h) Change the direction of the DMA transfer to PCI-to-Local for DMA CH0, by modifying the Descriptor Pointer (90h) value from 8 to 0.

34

i)

Click the [Start Transfer] button to perform a DMA transfer again

j)

Type in dl s0 to compare the data from step G.

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

7.

CPLD Verilog Code

7.1 Verilog Code //============================================================== // // 8/8/2005 // // Synchronous SRAM controller for PLX PEX 8311 mode C and J. // 128K byte (32K x 32 bit) synchronous SRAM is used. // The memory map for the sync. SRAM is 0000_0000 - 0001_FFFFh. // A partial memory decode is used. The decode is only involved // address lines A31 to A28 (or A31-A29 and LD28 in J mode) // // //=============================================================== `timescale 1ns/100ps module sramctr82xx ( clk,adsn,blastn,lwdrdn,lhold,lbr,lben,adds_in,adds_4msb, readyn,btermn,sramcsn,sramoen,lholda,lbg,sram_adds, sram_bwn,csn); input input input input input output output output output output reg reg reg tri

clk,adsn,blastn,lwdrdn,lhold; [1:0] lbr; [3:0] lben; [9:2] adds_in; [31:28] adds_4msb; readyn,btermn,sramcsn,sramoen,lholda; [1:0] lbg; [9:2] sram_adds; [3:0] sram_bwn; [3:0] csn; [9:2] [1:0]

sram_adds; lbg; sramcsn,sramoen,lholda; readyn,btermn;

// internal veriables reg [3:0] a31_28; reg [1:0] state; reg oer,oeb; BUFE tt1(.O(readyn),.E(!oer),.I(oer)); BUFE tt2(.O(btermn),.E(!oeb),.I(oeb)); // chip selects // Four uppermost address lines, A31-A28, are used to generate four // chip select signals for the board. They are CS[3:0] with addresses // // csn_0: 1000_0000h // csn_1: 2000_0000h // csn_2: 3000_0000h // csn_3: 4000_0000h

wire [3:0] csn = (adds_4msb == 4'b0001) ? 4'b1110: (adds_4msb == 4'b0010) ? 4'b1101: PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

35

(adds_4msb == 4'b0011) ? 4'b1011: (adds_4msb == 4'b0100) ? 4'b0111: 4'b1111; // byte enable encode for SRAM write cycles wire [3:0] sram_bwn =({lwdrdn,a31_28}=='b1_0000) ? lben[3:0] : 4'b1111; // store the upper address LA31 - LA28 always @ (posedge clk) if (!adsn & (adds_4msb==4'b0000)) a31_28[3:0] <= adds_4msb[31:28];

// SRAM control state machine parameter s0=2'b00, s1=2'b01, s2=2'b10, s3=2'b11; always @ (posedge clk) casex (state) s0: begin sramoen <=1; oeb <='b1; if (!adsn && !adds_4msb) begin sram_adds[9:2] <= adds_in[9:2]; sramcsn <= 0; if (lwdrdn) oer <= 'b0; else oer <= 'b1; state <= s1; end else begin oer <= 'b1; sramcsn <= 1; state <= s0; end end

s1: if (lwdrdn && (!blastn)) begin sram_adds[9:2] <=sram_adds[9:2]+1; sramoen <=1; sramcsn <=1; oer <='b1; oeb <='b1; state <= s0; end else if (lwdrdn && blastn) begin if (sram_adds[9:2]== 'hfe) 36

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

begin oeb <='b0; sram_adds[9:2] <= sram_adds[9:2]+1; state <= s3; end else begin sram_adds[9:2] <= sram_adds[9:2]+1; sramoen <=1; sramcsn <=0; oer <='b0; oeb <='b1; state <=s1; end end else begin sram_adds[9:2] <=sram_adds[9:2]+1; sramoen <=0; sramcsn <=0; oer <='b0; oeb <='b1; state <= s2; end

s2: if ((!lwdrdn) && (!blastn)) begin sramoen <=1; sramcsn <=1; oer <='b1; oeb <='b1; state <=s0; end else begin if (sram_adds[9:2]=='hff) begin oeb <='b0; sram_adds[9:2] <= sram_adds[9:2]+1; state <=s3; end else begin sram_adds[9:2] <= sram_adds[9:2]+1; sramoen <=0; sramcsn <=0; oer <='b0; oeb <='b1; state <=s2; end end

s3: begin PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

37

sramcsn <=1; oer <='b1; oeb <='b1; state <=s0; end default: state <=s0; endcase always @(posedge clk) begin if (lhold) lholda <= lhold; else lholda <= 0; if (!lhold && lbr[1]) lbg[1] <= lbr[1]; else lbg[1] <= 0; if (!lhold && !lbr[1] && lbr[0]) lbg[0] <= lbr[0]; else lbg[0] <= 0; end endmodule

38

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

8.

References

The following is a list of documentation to provide further details. ƒ

ƒ

PLX Technology, Inc. 870 Maude Ave. Sunnyvale, CA 94085 USA Tel: 408-774-9060 Tel: 800-759-3735 Fax: 408 774-2169 http://www.plxtech.com ƒ

PEX 8311 Data Book, Version xx or higher

ƒ

PEX 8311RDK Hardware Reference Manual

PCI Special Interest Group (PCI-SIG) 5440 SW Westgate Drive #217 Portland, OR 97221 USA Tel: 503-291-2569 Fax: 503-297-1090 http://www.pcisig.com ƒ

PCI Express Card Electromechanical (CEM) Specification, Revision 1.0a

ƒ

PCI Express-to-PCI Bridge Specification 1.0

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

39

9.

Bill of Materials / Schematics

The following pages contain the PEX 8311RDK bill of materials and schematics. Table 9-1. PEX 8311RDK Bill Of Materials Item Qty Man Man's Part # # SURFACE MOUNT COMPONENTS

Des

Package Type

1

8

Panasonic

ECJ1VB1H102K

Cap, Ceramic, 0.001 uF, 10%, 50V, X7R

0603

2

24

Kemet

C0603C103M5U AC

Cap, Ceramic, 0.01 uF, 50 V, 20%

0603

ECJ1VB1E104K

Cap, Ceramic, 0.1 uF, 10%, 16V, X7R

ECJ1VB1C105K, ECJ1VF105Z T494B106K016A T T491D474M016A T TSM-110-01-TDV

Cap, Ceramic, 1.0 uF, 16 V Cap, Tantalum, 10 uF, 16V Cap, Tantalum, 47uF,16V Header, 10 x 2 pins, 0.1", SMT Header, 50 x 2 pins, .25mm, SMT, Shrouded

3

47

Panasonic

4

2

Panasonic

5

10

Kemet

6

2

Kemet

7

6

Samtec

8

1

AMP

9

4

Chicago

10

3

Chicago

11

1

Steward

L10805E400R

12

1

CTS Corp

742C083271JTR

13

13

CTS Corp

742C083103JTR

14

30

Panasonic

ERJ3GEY0R00V

15

2

Panasonic

ERJ6GEY0R00V

6-104655-1 CMD1721VRC/TR8 CMD1721VGC/TR8

16

1

Panasonic

ERJ3RQF0r180V

17

5

Panasonic

ERJ3GEYJ330V

18

5

Panasonic

ERJ3GEYJ101V

19

2

Panasonic

ERJ3GEYJ331V

20

22

Panasonic

ERJ3GEYJ102V

21

1

Panasonic

ERJ3GEYJ122V

22

26

Panasonic

ERJ3GEYJ103V

0603

Schematic Reference C16, C18, C20, C26, C28, C30, C32, C200 C6, C10, C46, C48, C52, C54, C56, C58, C60, C62, C64, C66, C68, C70, C72, C74, C79, C83, C84, C85, C89, C90, C91, C155 C1, C2, C3, C8, C12, C14, C15, C17, C19, C22, C23, C24, C25, C27, C29, C31, C36, C37, C38, C39, C40, C41, C42, C44, C45, C47, C49, C50, C53, C55, C57, C59, C61, C63, C65, C67, C69, C71, C73, C75, C77, C80, C81, C82, C86, C87, C88

Subcon.

Subcon. Part #

Taiyo-Yuden

UMK107B102KZT

0603

C5, C11

Taiyo-Yuden

EMK107BJ105M A-B

CASE B

C4, C7, C9, C21, C33, C34, C35, C51, C76, C78

AVX

TAJ B 106M016R

CASE D

C13, C43

AVX

TAJ C476M020R

SMT

LAH1, LAH2, LAH3, LAH4, LAH5, LAH6

SMT

J3

LED, SMT, Red

0805

LED1, LED2, LED3, LED4

LED, SMT, Green

0805

LED5, LED6, LED8

0805

L1

0603x4

RN1

NIC Compnents

NSRN06I4G271T RF

NIC Components

NSRN06I4J103T RF

NIC Components

NRC06Z0

Ferrite chip, 47 uH, 500mA Resistor Array, x4, 270 Ohms, 5%, 0.1W Resistor Array, x4, 10K Ohms, 5%, 0.1W

0603x4

Resistor, 0 ohms (Jumper), 5%, 0.1 W

0603

RN2, RN3, RN4, RN5, RN6, RN7, RN8, RN9, RN10, RN11, RN12, RN13, RN14 R9, R10, R11, R12, R13, R34, R35, R53, R63, R66, R74, R76, R84, R88, R94, R96, R100, R106, R109, R111, R113, R122, R123, R129, R130, R131, R132, R133, R134, R135

Resistor, 0 ohms (Jumper), 5%. 1/8W Resistor, 0.18 ohms, 1%, 0.1W Resistor, 33 ohms , 5%, 0.1 W Resistor, 100 ohms , 5%, 0.1 W Resistor, 330 ohms, 5%, 0.1W

0603

R24

0603

R54, R55, R56, R57, R58

0603

R28, R29, R30, R31, R127

0603

R99, R125

Resistor, 1K ohms , 5%, 0.1 W

0603

R5, R6, R8, R14, R15, R16, R17, R18, R19, R41, R65, R67, R68, R69, R72, R73, R78, R79, R80, R81, R82, R639

0603

R124

0603

R3, R4, R25, R26, R36, R37, R38, R42, R43, R44, R45,

Resistor, 1.2K ohms , 5%, 0.1 W Resistor, 10K ohms , 5%, 0.1 W

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

0805

R21, R23

NIC Components NIC Components NIC Components NIC Components NIC Components NIC Components NIC Components NIC Components

NRC10Z0 NRC06F0R18TR F NRC06J330TRF NRC06J101TRF NRC06J331TRF NRC06J102TRF NRC06J122TRF NRC06J103TRF

41

Item Qty #

Man

Man's Part #

Des

Package Type

Subcon.

Subcon. Part #

Thru-Hole

JP1, J7, J8, J9

AMP

Thru-Hole

JP2, JP3, JP4, JP5

AMP

Thru-Hole

J1

Thru-Hole

J2

Thru-Hole

J4

Thru-Hole

U2, U6, U8

Schematic Reference R47, R48, R50, R89, R90, R91, R92, R98, R101, R102, R104, R105, R107, R638, R1147

23

1

Omron

B3S1002

Switch, SPST, momentary, vertical

24

1

PLX Technology, Inc.

PEX 8311

IC, PEX8311

25

1

National Semiconductor

LP2992IM5-1.5

IC, LDO Regulator, 1.5 V, 250 mA

26

1

National Semiconductor

LMS1585ACS3.3

27

1

Semtech

LT1963AEXT-25

28

1

Maxim

MAX6306UK30D 1-T

29

1

Cypress Semiconductor

CY2305SC-1

30

1

Xilinx

XC9572XL5TQ100C

31

1

Samsung

K7B403625B

IC, LDO Regulator, 3.3V, 3A IC, LDO regulator, 2.5V, 1A IC, Reset Controller, MAX6306UK30D1-T IC, Clock Buffer, CY2305 IC, CPLD Programmable Logic XC9572XL5TQ100C IC, Synchronous SRAM, 4 Mbit, 128Kx36, FlowThrough

SMT BGA, 21x21 mm, 20x20 ball, 1.0mm pitch NS Package Number MF05A

SW1 U1

U3 U4

SOT-223

U9

SOT-23, 5 pin

U5

SOIC, 8-pin

U7

TQFP, 100 pins (square)

U10

TQFP, 100 pins, 14x20 mm

U11

THROUGH-HOLE COMPONENTS 32

4

Molex

22-28-4020

33

4

Molex

22-28-4030

34

1

Molex

22-28-4060

35

1

Molex

22-28-4090

36

1

Molex

53109-0410

37

3

Mil-Max

110-93-308-41-001

Header, 2 x 1 pins, 0.1", vert., no shroud Header, 3 x 1 pins, 0.1", vert., no shroud Header, 6 x 1 pins, 0.1", vert., no shroud Header, 9 x 1 pins, 0.1", vert., no shroud 5.08mm (.200") Pitch Disk Drive Power Connection System Header, Right Angle, with Strap Standard Polarization, 4 Circuits Socket, 8-pin dip, 0.3", solder tail, low-profile

COMPONENTS THAT ARE HAND-ASSEMBLED 38

1

CTS Corp

39

1

Atmel

40

1

Atmel

41

1

Keystone

42

OSC, 66.666 MHz clock oscillator, 3.3V, 50ppm, 4060% duty cycle IC, Serial AT25640A-10PI-2.7 EEPROM, SPI, 64K, AT25640 IC, Serial AT93C56A-10PU-2.7 EEPROM, 3-wire, AT93C56/66A PCI Bracket, 9203 Blank MXO45HS-3C66M6666

Half-size DIP, 8-pin

U8

DIP, 8-pin

U2

DIP, 8-pin

U6

Ecliptek

EP1345HSPD66.666M

BRACKET1

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

Item Qty # 42

2

43

6

Man

Man's Part #

Spaenaur

492-100

Des

Package Type

Phillips, 4-40, 1/4", PH screw (for PCB bracket) Jumper shunts, for 0.1" hdr.

Schematic Reference

Subcon.

Subcon. Part #

SCREW1, SCREW2 J7, J8, J9, JP3(1-2), JP4(1-2), JP5(1-2)

MISCELLANEOUS COMPONENTS PEX 8311RDK PCB, p/n 90-0058000-A 8" x 10" anti-static 45 1 Velostat 2100R/8X10 bag PARTS THAT ARE NOT POPULATED (DO NOT KIT) Header, 5 x 2 pins, 46 1 Molex 10-88-1105 0.1", vert., no shroud Header, 7 x 2 pins, 47 1 Comm Con 2422-14G2 0.1", vert, keyed shrd. IC, LDO regulator, 48 1 Semtech EZ117-2.5 2.5V, 1A Resistor, 0 ohms 49 2 Panasonic ERJ6GEY0R00V (Jumper), 5%. 1/8W T494B106K016A Cap, Tantalum, 10 50 3 Kemet S uF, 16V ICS Tech IC, PCI-Express 51 1 (www.icst.c ICS557G03 Clock Source, om) ICS557-03 CB3LV-3C52 1 CTS Corp XTAL, 25 MHz, SMD 25M0000 OSC, 66.666 MHz MXO45HS-3Cclock oscillator, 53 1 CTS Corp 66M6666 3.3V, 50ppm, 4060% duty cycle Socket, 8-pin dip, 110-93-308-4154 1 Mil-Max 0.3", solder tail, low001 profile Resistor, 10 ohms , 55 1 Panasonic ERJ3GEYJ100V 5%, 0.1 W Resistor, 33 ohms , 56 4 Panasonic ERJ3GEYJ330V 5%, 0.1 W Resistor, 49.9 ohms, 57 4 Panasonic ERJ3EKF49R9V 1%, 0.1W Resistor, 475 Ohms, 58 1 Panasonic ERJ3EKF4750V 1%, 0.1W Resistor, 10K ohms , 59 8 Panasonic ERJ3GEYJ103V 5%, 0.1 W Cap, Ceramic, 10 60 2 Panasonic ECJ1VC1H100D pF, 50V, +/- 0.5 pF C0603C103M5U Cap, Ceramic, 0.01 61 2 Kemet AC uF, 50 V, 20% Cap, Ceramic, 0.1 62 1 Panasonic ECJ1VB1E104K uF, 10%, 16V, X7R 44

63

1

18

Panasonic

ERJ3GEY0R00V

BAG1 Thru-Hole

FAI

JP6 JP7

OUPIIN

3112-14GSB

SOT-223

U14

0805

R22, R27

NIC Components

NRC10Z0

CASE B

C96, C98, C100

AVX

TAJ B 106M016R

TSSOP-16 pins

U12

SMT, 3.2x2.5mm

Y1

Half-size DIP, 8-pin

U13

Ecliptek

EP1345HSPD66.666M

Thru-Hole

U13

0603

R136

0603

R137, R141, R145, R148

Resistor, 0 ohms (Jumper), 5%, 0.1 W

0603

R138, R142, R143, R147

0603

R149

0603

R32, R33, R139, R140, R144, R146, R147,R641

0603

C94, C95

0603

C92, C93

0603

C97

0603

R59, R60, R61, R62, R64, R83, R86, R75, R77, R85, R87, R93, R95, R97, R103, R108, R110, R112

NIC Components NIC Components NIC Components NIC Components NIC Components

NIC Components

NRC06J100TRF NRC06J330TRF NRC10F49R9TR F NRC10F4750TRF NRC06J103TRF

NRC06Z0

Resistor, 4.7K NIC 0603 R39, R49, R51 NRC06J103TRF ohms , 5%, 0.1 W Components NOTE: NOT POPULATED NO VALUE COMPONENTS FROM SHEETS 8 TO 12 OF THE SCHEMATICS ARE NOT LISTED. SEE SECTION 4.4.2 FOR COMPONENT VALUES NOTE: OTHER NOT POPULATED COMPONENTS ARE NOT LISTED AT THIS TIME Customer Name: PLX PLX Part #: 91-0058-000-A Product Name: PEX 8311RDK 64

3

Panasonic

ERJ3GEYJ472V

PEX 8311RDK Hardware Reference Manual, Version 0.90 © 2005 PLX Technology, Inc. All rights reserved.

43

A

Table Of Contents

4

01: 02: 03: 04: 05: 06: 07: 08: 09: 10: 11: 12: 13: 14: 15:

Cover Page PEX8311 PCI Express Bus PLX8311 Local Bus CPLD and SBSRAM Test Headers PLX Option Module Connector Catalyst Midbus and PCIE Clock Gen FPGA Footprint FPGA Side A Option Resistors FPGA Side B Option Resistors FPGA Side C Option Resistors FPGA Side D Option Resistors Pads Prototype Footprint NC Balls

B

C

D

E

Block Diagram

Revision History Date 12-08--05

On-Board Prototyping Area - 144-pin PLCC Footprint for Altera or Xilinx FPGA - SMD device footprints - Power Regulator circuit (un-populated) - Thru-hole grid, 20x10, 0.1" spacing

Xilinx XC9572XL CPLD - SBSRAM controller - Chip Selects - Local Bus Arbiter

Test Headers

Summary of Changes Release 1.0

Custom Daughter Card Mounting Area

4

Daughter Board Conn. use AMP p/n 6-104652-0

Samsung K7B403625B Synchronous Burst SRAM (Flow-Through Outputs) 512 Kbytes

Daughter Board Header AMP p/n 6-104655-1

JTAG

32bit, 66.666Mhz PLX Local Bus

93CS56/66 u-Wire EEPROM (Local Bus Config.)

3

JTAG

LCLK Dist.

PEX 8311

LCLK Osc.

Power Regulators +3.3 V +2.5 V +1.8 V

On-board Reset Gen.

AT25640A SPI EEPROM (PCIE Config.)

3

PCI Express Clock Gen. (not populated)

Catalyst Mid-Bus LAI Footprint

PCI Express X1 Card-Edge Connector

+12 V +3.3 V

+12 V +5.0 V

ATX HDD Pwr. Conn Molex 53109-0410

2

2

This schematic includes minor board errata's which are not implemented in the PCB layout. See PEX8311RDK Errata Rev. 1.0, Dec. 2005 for details.

© 2005 PLX Technology, Inc. All rights reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products. PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc. 1

1

Other brands and names are the property of their respective owners.

PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com Title

PEX8311RDK-Lite

A

B

C

D

Size Custom

Document Number

Date:

Wednesday, December 14, 2005

Rev 000

91-0058-000-A Sheet E

1

of

15

A

B

3.3VCC

8311_3.3V

1.5VCC

J8

J7

D

E

8311_1.5V

1

1

C

PERp0

2

PERp0

PERn0

2

PETp0 PETn0

7

PERn0

7

PETp0

7

PETn0

7 8311_3.3V

PCIE3.3VCC

PCIE12VCC

PCIE3.3VCC

8311_3.3V

8311_1.5V 8311_PLL1.5VCC

4

4

C1

5

PCIE3.3VCC R5 R6

D7 E5 F5

WAKEIN#

WAKEIN# ROOT_COMPLEX#

1K 1K

B2 A18 D2 A3 A10 N1 F3 D10

PWR_OK PLXT1

R7 TP1 0_NP

R8 R9 R10 R11

PERST#

1K 0 0 0 PERST_8311#

0.1uF B12 B13 B14 B15 B16 B17 B18

RSVD GND GND REFCLK+ PETp0 REFCLKPETn0 GND GND PERp0 PRSNT2# PERn0 GND GND

A12 A13 A14 A15 A16 A17 A18

R12 R13

PETp0 PETn0

2 0.1uF

PETp0C 1 PETn0C

PERp0 PERn0

C2

WAKEIN# ROOT_COMPLEX# PWR_OK PLXT1 PLXT2 TEST BUNRI BTON

C3 H1 H2

PERST# REFCLK+ REFCLK-

J1 K2 G1 F2

PETp0 PETn0 PERp0 PERn0

R1 1

WAKEOUT#D1

R2 0_NP

2

J2

PEX8311

2 C1 B1 D3 A1

EECS# EECLK EEWRDATA EERDDATA

K3 L4 L3 M3

BAR0ENB#

E1

TCK TMS TDI TRST# TDO ITDO SMC TMC TMC1 TMC2

WAKEOUT#

0_NP

C3 0.1uF

PCI Express x1 Edge

A13 A11 A14 B14 C14 C15 V4 E2 V3 E3

1.5VCC

U3

REFCLK-

BAR0ENB#

GND

BYPASS

TDO ITDO

J1

JTAG Port R14 R15 R16 R17

R18

R19

1K

1K

1K

1K

1K

1K

R639 1k

R638

BAR0ENB#

+12V

4

R21 0

0_NP

JP1

U4 LMS1585ACS-3.3

C6 R22

2

R20

PLXT1

0_NP

0.01uF

3

VIN

C8

+

VOUT

1.8A max.

2

10uF

C155 0.01uF C10

C9 10uF ceramic

1

PLL Filter

0.01uF

PCIE3.3VCC

PCIE3.3VCC

0.1uF

1.5VCC

R23 8311_PLL1.5VCC

1uF

C12

1

C11

R25 10K

0.1uF R27

3

0_NP

4

8311_1.5V

C19 0.1uF

C20 0.001uF

R28 R29 R30 R31

100 100 100 100

3 1

8311_3.3V

2 JP3

GPIO0

5,9,10 LED1

2

GPIO1

5,9,10 LED2

LED

LED2

LED3

LED

LED3

LED

LED4

1 2

PCIE3.3VCC C30

C31

1

C29

1

C28

1

1

1

1

1

1

3 C27

GPIO2

0.1uF

2

0.001uF

2

0.1uF

2

0.001uF

2

2

2

2

2

0.1uF

0.001uF

2 3

C34 10uF

C35 10uF

1

LED GPIO3

5,9,11

RN1 274

PLX TECHNOLOGY, INC. C42 0.1uF

870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

4 3 2 1

C43

Title

+ 2

0.1uF

1

C41

2

0.1uF

1

C40

2

0.1uF

1

C39

2

0.1uF

1

C38

2

0.1uF

1

C37

2

0.1uF

1

C36

2

1

1

8311_1.5V

Place one cap. to each edge connector's 3.3V pin.

2

C33 10uF

User Accessible Reset Circuit

JP5 1

0.001uF

PEX8311 PCI Express bus

47uF

Size Custom

Document Number

Date:

Wednesday, December 14, 2005

PLACE CLOSE TO THE CHIP A

PERST_8311#

5,10,11 LED4

C32

1

0.1uF

2

LED1

JP4

C26

GND

1

3

C25

1

JP2

0.1uF

Place close to the edge connector

5

5 6 7 8

0.001uF

1

C18

2

0.1uF

1

C17

2

0.001uF

1

C16

2

0.1uF

1

C15

2

0.001uF

1

C200

2

0.1uF

1

1

C14

2

2

C24

2

1 0.1uF

1

1

C23

2

0.1uF

2

2

1

1 2

C22

RST_IN

VCC RESET#

MAX6306UK30D1-T

PCIE3.3VCC

C21 10uF

MR#

SW PUSHBUTTON PERST#

PCIE12VCC

R26 10K

U5

2

SW1

2

47uF

2

2

PCIE3.3VCC 1

C13 +

1

R24

2

L1.5R

1

2

2

3.3VCC 0

1.4 (include L1 DC resistance) 1 2 1

L1

47uH (>30mA)

+

10k

ITDO

PCIE12VCC

C7

1

5

1 2 3 4 5 6

PCIE3.3VCC

C4 10uF Ceramic

LP2992

2

BAR0ENB#

TCK TMS TDI

5

1

2

VCC HOLD# SO GND

2

ON/OFF

CS# SCK SI WP#

8 7 2 4

PCIE3.3VCC

GND

1

3

VOUT

2

C5 1uF

VIN

R4 10K

AT25640

EERDDATA

250mA Max. 1

U2 1 6 5 3

EECS# EECLK EEWRDATA

REFCLK-

REFCLK+

7

REFCLK+

7

R3 10K

1

PCIE3.3VCC

GPIO0 GPIO1 GPIO2 GPIO3

3

F11 F10 F9 F8 F7 A2 B15 W3 W4 P5 N5 M5 L5 K5 J5 H5 G5 M4 K4 J3 F4 H4 G4 F1 G2 K1

3

0 0

GPIO0 GPIO1 GPIO2 GPIO3

VDD3.3 VDD3.3 VDD3.3

1

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

2

PRSNT1# +12V +12V GND JTAG2 JTAG3 JTAG4 JTAG5 +3.3V +3.3V PERST#

PCIE3.3VCC

1

+12V +12V RSVD GND SMCLK SMDAT GND +3.3V JTAG1 3.3Vaux WAKE#

PCIE3.3VCC

VDD_P

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AVSS VSS_C VSS_P0 VSS_P1 VSS_R VSS_RE VSS_T

2

1

P1

VDD1.5 VDD1.5 VDD1.5 VDD1.5 VDD1.5 VDD1.5 VDD1.5 VDD1.5 VDD_T VDD_R AVDD

VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3

PRSNT

C2 C9 C13 D6 L1 L2 M1 W5 J4 H3 G3

D8 D9 E9 E15 F15 G15 E16 E17 F16 F17

U1A

B

C

D

Rev 000

91-0058-000-A Sheet E

2

of

15

A

2.5VCC

B

C

D

E

8311_2.5V 3.3VCC

3.3VCC

J9 RN2 1

2

LBE#[3:0]

4,5,6,12

3.3VCC

LA[31:2]

4,5,6,9,10,11,12

DP[3:0]

5,11

4

MODE0 0 1 Reserved 0 Reserved 1

4,5,6,9,10,11,12

LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 LD26 LD27 LD28 LD29 LD30 LD31

LD[31:0]

MODE

MODE1 0 0 1 1

C R33 10K_NP J

R32 10K_NP

LBE#0 LBE#1 LBE#2 LBE#3

R32 and R33 should not be installed by default.

MODE0

R34

0

MODE1

R35

0

RN3

1 2 3 4

8 7 6 5

LA2 LA3 LA4 LA5

742-08-3-103-J-XX ADS# BLAST# READY# WAIT#

RN5

1 2 3 4

8 7 6 5

LA6 LA7 LA8 LA9

R52

C47

C48

C49

0.01uF

0.1uF

0.01uF

0.1uF

K20 K19 K18 K17 L20 L19 L18 L17 M20 M19 M18 M17 N20 N19 N18 N17 P20 P19 P18 P17 R20 R19 R18 R17 T20 T19 T18 T17 U20 U19 V20 V19

F19 F20 F18 H17 U18 J19

ADS# BLAST# READY# WAIT# LW/R# BTERM#

CCS# LINTo# LINTi# LSERR# BREQi BREQo DMPAF/EOT# BIGEND# USERo/LLOCKo# USERi/LLOCKi# DREQ0# DREQ1# DACK0# DACK1#

D17 E19 E20 J18 G18 G17 C18 D18 D19 D20 C19 B17 C20 B18

CCS# LINTo# LINTi# LSERR# BREQi BREQo DMPAF/EOT# BIGEND# USERo/LLOCKo# USERi/LLOCKi# DREQ0# DREQ1# DACK0# DACK1#

MODE0 MODE1

H19 H20

MODE0 MODE1

EESK EEDI/EEDO EECS BD_SEL# IDDQEN# PMEIN# PMEOUT#

A19 B20 A20 B19 V10 C16 B10

EESK EEDI/EEDO EECS BD_SEL# IDDQEN# PMEIN# PMEOUT#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

F13 F12 F6 G7 G6 H6 J6 K6 L6 M6 N6 P6 R6 R7 R8 R9 R10 R11 R12 R13 V1 W1 Y1 W2 Y2 Y3 Y4 R5 U5 T5 U6 R14

LBE0# LBE1# LBE2# LBE3#

Y5 C17 H18 J17 T16 U15 V9

VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5

G16 H16 J16 K16

VDD3.3 VDD3.3 VDD3.3 VDD3.3

N16 P16 R16 T15 U14 V14 T12 U11 U10

VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3 VDD3.3

C52

C53

C54

C55

0.01uF

0.1uF

0.01uF

0.1uF

Serial EEPROM

4,5 4,5

ADS# BLAST# READY# WAIT# LW/R# BTERM#

10K 4,5,6,11 4,5,6,11 4,5,6,12 5,6,12 4,5,6,12 4,5,6,11

LINTi# LSERR# DMPAF/EOT# BIGEND#

742-08-3-103-J-XX 742-08-3-103-J-XX RN8 1 8 2 7 3 6 4 5

3.3VCC

C44 U6 EECS EESK EEDI/EEDO

1 2 3 4

CS SK DI DO

VCC PRE PE GND

8 7 6 5

PRER37 PE R38

10K

0.1uF

8 7 6 5

LA10 LA11 LA12 LA13

RN9 LA14 LA15 LA16 LA17

1 2 3 4

8 7 6 5

742-08-3-103-J-XX

RN10 USERo/LLOCKo# USERi/LLOCKi# LRESET#

8 7 6 5

RN11

1 2 3 4

8 7 6 5

LA18 LA19 LA20 LA21

1 2 3 4

8 7 6 5

4.7K_NP 742-08-3-103-J-XX RN12 DREQ0# DREQ1# DACK0# DACK1#

RN13

1 2 3 4

8 7 6 5

LA22 LA23 LA24 LA25

742-08-3-103-J-XX

Optional for debug

3.3VCC

LHOLD

R46

0_NP

BD_SEL#

R41

1K

BREQi BREQi BREQo

R42 R43

10K 10K

LHOLDA LHOLD

R44 R45

10K 10K

READY#

5,11,12 5

R49

1 2 3 4

8 7 6 5

3

742-08-3-103-J-XX RN14 LA26 LA27 LA30 LA31

1 2 3 4

8 7 6 5

742-08-3-103-J-XX

LHOLDA LA28 LA29

10K

PMEIN# PMEOUT#

1 2 3 4

742-08-3-103-J-XX

742-08-3-103-J-XX

10K

93CS56L or 66L(8DIP-Socket)

R39

CCS# 11 LINTo# 5,6,9 LINTi# 5,6,12 LSERR# 5,10 BREQi 5,6,9,11 BREQo 5,6,9,11 DMPAF/EOT# 4,5,6,11 BIGEND# 5,11 USERo/LLOCKo# 5,6,9 USERi/LLOCKi# 5,6,9,10 DREQ0# 4,5,6,11 DREQ1# 4,5,6,12 DACK0# 4,5,6,10 DACK1# 4,5,6,11

R47

1 2 3 4

R36

LHOLD LHOLDA

RN7

LW/R# BTERM# CCS# LINTo#

4.7K_NP

R48 R50

10K 10K

R51 4.7K_NP 3.3VCC

R1147

R51 should not be installed by default. For J Mode, R51 has to be installed and R50 remove.

10K

3.3VCC 2

C45

0.1uF

Clock Circuit

U7

3.3VCC U8 8

VCC

4

GND

OUT

5

NC

1

1

REF

C51 C50

+ 10uF

0.1uF

CY2305

osc_halfsize (Socket)

CLKOUT CLK1 CLK2 CLK3 CLK4

R54 R55 R56 R57 R58

8 3 2 5 7

33 33

LCLK1 33 33 33

SRAM_CLK

4

CLK_66MHZ LCLK_T POM_CLK

4 5,9,12 6

A17 A16 B16 D15 D14 D13 D12 E14 E13 E12 E11 E10 E8 E7 F14 H15 J15 K15 N15 P15 R15 T14 T13 U13 V13 U12 V12 T11 T10 T9 T8 U8 T7 T6 U9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

C46

ADS# BLAST# READY# WAIT# LW/R# BTERM#

PEX8311

CLKOUT CLKIN

R53

2

LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 LA31

A8 A15 0

8311_2.5V

LHOLD LHOLDA

5,6,12

4

742-08-3-103-J-XX

6

CLKOUT 0_NP

LHOLD LHOLDA

G20 G19

LRESET#

VCC

TP2

W19 W20 Y20 Y19

LRESET# LCLK1

GND

8311_3.3V

LBE#0 LBE#1 LBE#2 LBE#3

E18 J20

8 7 6 5

4

CLKIN

Y18 W18 V18 Y17 W17 V17 U17 Y16 W16 V16 U16 Y15 W15 V15 Y14 W14 Y13 W13 Y12 W12 Y11 W11 V11 Y10 W10 Y9 W9 Y8 W8 Y7

3.3VCC

LRESET# LCLK

DP0 DP1 DP2 DP3

8311_3.3V

8311_2.5V

PCIE3.3VCC

1 C56

C57

C58

C59

C60

C61

C62

C63

C64

C65

C66

C67

C68

C69

C70

C71

C72

C73

C74

C75

0.01uF

0.1uF

0.01uF

0.1uF

0.01uF

0.1uF

0.01uF

0.1uF

0.01uF

0.1uF

0.01uF

0.1uF

0.01uF

0.1uF

0.01uF

0.1uF

0.01uF

0.1uF

0.01uF

0.1uF

C76

C77

VIN

2

+ 10uF

2.5VCC

U9 LT1963AEXT-25

1

GND

LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 LA31

3

7

L16 L15 M16 M15

1 2 3 4

RN6

LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 LD26 LD27 LD28 LD29 LD30 LD31 DP0 DP1 DP2 DP3

8 7 6 5

742-08-3-103-J-XX

RN4

742-08-3-103-J-XX U1C

1 2 3 4

VOUT

3

1

1A max. C78

C79

+

PLX TECHNOLOGY, INC.

0.01uF

10uF

870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com

0.1uF Title

PEX-8311 Local bus

A

B

C

D

Size Custom

Document Number

Date:

Wednesday, December 14, 2005

Rev 000

91-0058-000-A Sheet E

3

of

15

A

B

C

D

E

Synchronous SRAM and Controller Circuit R59-R62, and R64 should not be installed by default 3,5,6,11 DREQ0# 3,5,6,12 DREQ1# 3,5,6,10 DACK0#

R59

0

DREQ1#

R60

0

DACK0#

R61

0

DACK1#

R62

0

R63

0

READY#

DMPAF/EOT#

R64

0

R66

0

BTERM#

3,5,6,12 LBE#[3:0]

R74 LA31 LD31 R75 R76

PA35 PA36 LBE#0 PA38 LBE#1 PA40 LBE#2 PA42 LBE#3 PA44 PA46 PA48 3,5,6,9,10,11,12 PA50 PA52 PA54 0 PA56 PA58 AA31 PA60 PA62 0 PA64 PA66 0

LA30 LD30

AA30 R77 R84

0 0

LA29 LD29

AA7 MA9 LW/R# LBE#2 MA7 LBE#3 AA9 MA8

CLK_66MHZ

AA28

PA71

R86

3.3VCC

2

R87

0

LA2 R88

0

LD3

R93

0

LA3 R94

0

LD4

R95

0

LA4 R96

0

R97

0

LD5

LA5 R100 LD6

R103

0 0

R108

0

LA7 R109

0

R110

0

LA8 R111

0

LD8

IO/GCK1 IO/GCK3 IO/GTS2

65 67 71 72 68 76 77 70 66 81 74 82 85 78 89 86 90 79

TCK TDI TDO TMS

48 45 83 47

SRAM_BW_0 LBR0 SRAM_BW_1 SRAM_BW_2 SRAM_BW_3 AA30 SRAMCS_

AA28 SRAMOE_

LBE#1 MA2 LBE#0 MA4 AA5

PA20 PA9 PA1 PA10 PA12 PA3 PA14 PA16 PA5 PA19 PA23 PA25 PA6 PA27 PA29 PA31 PA33 PA34 PA37 PA39 PA41 PA47 PA49 PA51 PA53 PA55 PA57 PA59 PA61 PA63 PA65 PA67 PA68 PA69

3.3VCC LBR0 LBG0 LBR1 LBG1

LBR0 LBG0 LBR1 LBG1

6 6 12 R68 9

R67

R69

R65

1K

1K

1K

1K

SA15 SA16

0_NPSA15 SA16 R71 0_NP R70

PA43

3

SRAM_CLK SRAMCS_ SRAMOE_ SRAM_BW_0 SRAM_BW_1 SRAM_BW_2 SRAM_BW_3

SRAM_CLK

PA45 R72 1K

R73 1K

3.3VCC R78 1K

J2 1 2 3 4 5 6 7 8 9

CPLD_TCK CPLD_TDO CPLD_TDI CPLD_TMS R89 R90 R91 R92

R79 1K

R80 1K

R81 1K

R112

0

LA9 R113

0

AA3

51 80 1 30 16 66 NC NC NC NC NC NC

15 41 65 91 4 11 20 27 54 61 70 77

SYNC_SRAM

88 97 83 84

GW# CE2 ADV# ADSP#

89 98 86 93 94 95 96

CLK CE# OE# BWa# BWb# BWc# BWd#

31 85 87 92 64

MODE ADSC# BWE# CE2# ZZ

R82 1K

128Kx36

DQa0 DQa1 DQa2 DQa3 DQa4 DQa5 DQa6 DQa7

52 53 56 57 58 59 62 63

LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7

DQb0 DQb1 DQb2 DQb3 DQb4 DQb5 DQb6 DQb7

68 69 72 73 74 75 78 79

LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15

DQc0 DQc1 DQc2 DQc3 DQc4 DQc5 DQc6 DQc7

2 3 6 7 8 9 12 13

LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23

DQd0 DQd1 DQd2 DQd3 DQd4 DQd5 DQd6 DQd7

18 19 22 23 24 25 28 29

LD24 LD25 LD26 LD27 LD28 LD29 LD30 LD31

3

K7B403625B

1x9 HDR, 0.1"oc 2

100-pin TQFP

R83 and R86 should not be installed by default

10K 10K 10K 10K

3.3VCC

CS_0#

CS_0#

6

AA4 3.3VCC AA5 SRAMCS_ SRAMOE_ SRAM_BW_0 SRAM_BW_1 SRAM_BW_2 SRAM_BW_3

AA6

R98

10K

LBR0 R101

R104

R99

330

10K R102

10K

R107

10K

10K R105

10K

AA7

AA8

AA9

1

LD[31:0]

SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16

XC9572XL-5TQ100C

3.3VCC LD9

37 36 35 34 33 32 100 99 82 81 44 45 46 47 48 49 50

VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16

3,5,6,9,10,11,12

or XC95144XL-5TQ100C

0

LA6 R106 LD7

AA2

27

IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 IOD8 IOD9 IOD10 IOD11 IOD12 IOD13 IOD14 IOD15 IOD16 IOD17 IOD18

21 31 44 62 69 75 84 100 2 7 19 24 34 43 46 73 80

0 LD2

0

4

0

LA28

IOB1 IOB2 IOB3 IOB4 IOB5 IOB6 IOB7/GTS1 IOB8 IOB9/GSR IOB10 IOB11 IOB12 IOB13 IOB14 IOB15 IOB16 IOB17

22 R83

PA70 AA29

R85

MA3

87 94 91 93 95 96 3 97 99 1 6 8 9 11 10 12 92

CPLD

LBG0 AA4 LBG1 LHOLD LHOLDA BLAST# BTERMN AA8 READYN

LA[31:2]

LA[31:2]

LD[31:0]

NC NC NC NC NC

AA2 AA31 CS_1# ADS# AA29 CS_2# AA6 CS_3#

IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 IOC8 IOC9 IOC10 IOC11 IOC12 IOC13 IOC14 IOC15 IOC16 IOC17 IOC18

3,5,6,9,10,11,12

14 38 39 42 43

CS_0#

IOA1 IOA2 IOA3 IOA4 IOA5 IOA6 IOA7 IOA8 IOA9 IOA10/GCK2 IOA11 IOA12 IOA13 IOA14 IOA15 IOA16

41 32 49 50 35 53 54 37 42 60 52 61 63 55 56 64 58 59

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

MA5

16 13 18 20 14 15 25 17 28 23 33 36 29 39 30 40

U11

5 10 17 21 26 40 55 60 67 71 76 90

AA3 MA6 LBR1

PA8 PA21 PA2 PA11 PA13 PA4 PA15 PA17 PA18 PA22 PA24 PA26 PA7 PA28 PA30 PA32

READY# BTERM# LHOLD LHOLDA LRESET# CS_3#

LA[31:2]

3.3VCC

VCC VCC VCC VCC VCC VCC VCC

U10

CLK_66MHZ ADS# BLAST# LW/R#

3,5,6,12 READY# 3,5,6,11 BTERM# 3,5 LHOLD 3,5 LHOLDA 3,5,6,12 LRESET# 10 CS_3#

3.3VCC

5 57 98 26 38 51 88

3,5,6,11 DMPAF/EOT#

3

DREQ0#

LD[31:0]

3,5,6,11 DACK1#

3 CLK_66MHZ 3,5,6,11 ADS# 3,5,6,11 BLAST# 3,5,6,12 LW/R#

4

GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC

4

3,5,6,9,10,11,12

For C mode (default), install R74,R76,R84,R88 , R94,R96,R100,R106,R109,R111 and R113, remove R75, R77 and R85,R87,R93,R95,R97, R103,R108,R110,and R112 For J mode, it is vice versa.

3.3VCC

C80

C81

C82

C83

C84

C85

C86

C87

C88

C89

C90

C91

0.1uF

0.1uF

0.1uF

0.01uF

0.01uF

0.01uF

0.1uF

0.1uF

0.1uF

0.01uF

0.01uF

0.01uF 1

PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com Title

SRAM & CPLD

A

B

C

D

Size Custom

Document Number

Date:

Wednesday, December 14, 2005

Rev 000

91-0058-000-A Sheet E

4

of

15

5

4

3,4,6,12 LBE#[3:0]

3,11

3,4,6,9,10,11,12

LAH1

LD[31:0]

LA[31:2]

BREQo BREQi DACK0# DREQ0# DACK1# DREQ1# DMPAF/EOT# USERi/LLOCKi# USERo/LLOCKo#

3,6,9,11 BREQo 3,6,9,11 BREQi 3,4,6,10 DACK0# 3,4,6,11 DREQ0# 3,4,6,11 DACK1# 3,4,6,12 DREQ1# 3,4,6,11 DMPAF/EOT# 3,6,9,10 USERi/LLOCKi# 3,6,9 USERo/LLOCKo#

LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 LD26 LD27 LD28 LD29 LD30 LD31

LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 LA31

C

1

PCIE3.3VCC DP0 DP1 DP2 DP3

3,4,6,9,10,11,12

2

DP[3:0]

LBE#0 LBE#1 LBE#2 LBE#3 D

3

1 3 5 7 9 11 13 15 17 19

+5V D16 D14 D12 D10 D8 D6 D4 D2 D0

2 4 6 8 10 12 14 16 18 20

D17 D15 D13 D11 D9 D7 D5 D3 D1 GND

BIGENDE# PMEIN# PMEOUT# WAKEIN# BAR0ENB# GPIO0 GPIO1 GPIO2 GPIO3

0_NP R114 0_NP R115 0_NP BIGEND# 3,11 R116 0_NP PMEIN# 3,11,12 R117 PMEOUT# 3 WAKEIN# 2 BAR0ENB# 2

LAH2

GPIO0 GPIO1 GPIO2 GPIO3

2,9,10 2,9,10 2,10,11 2,9,11

LA28 LA26 LA24 LA22 LA20 LA18 LA16 LA14

1 3 5 7 9 11 13 15 17 19

+5V D16 D14 D12 D10 D8 D6 D4 D2 D0

TP4

TP5

TP6

TP7

TP8

C

C

C

C

C

C

1

1

1

1

1

1

D

2 4 6 8 10 12 14 16 18 20

LA29 LA27 LA25 LA23 LA21 LA19 LA17 LA15

Logic Analyzer Header Logic Analyzer Header 0_NP R118 0_NP

LAH3 3,9,12

LCLK_T

1 3 5 7 9 11 13 15 17 19

LA12 LA10 LA8 LA6 LA4 LA2 LBE#2 LBE#0

+5V D16 D14 D12 D10 D8 D6 D4 D2 D0

2 4 6 8 10 12 14 16 18 20

D17 D15 D13 D11 D9 D7 D5 D3 D1 GND

LAH4

R119

0_NP 0_NP R120 R121

LA13 LA11 LA9 LA7 LA5 LA3 LBE#3 LBE#1

LD8 LD6 LD4 LD2 LD0 DP2 DP0 LA30

Logic Analyzer Header

1 3 5 7 9 11 13 15 17 19

+5V D16 D14 D12 D10 D8 D6 D4 D2 D0

LINTo# LINTi# LW/R# READY# ADS# LHOLD LD30 LD28 LD26

3,6,9 LINTo# 3,6,12 LINTi# 3,4,6,12 LW/R# 3,4,6,12 READY# 3,4,6,11 ADS# 3,4 LHOLD

1 3 5 7 9 11 13 15 17 19

+5V D16 D14 D12 D10 D8 D6 D4 D2 D0

D17 D15 D13 D11 D9 D7 D5 D3 D1 GND

2 4 6 8 10 12 14 16 18 20

LD9 LD7 LD5 LD3 LD1 DP3 DP1 LA31

C

Logic Analyzer Header

LAH5

TP3

D17 D15 D13 D11 D9 D7 D5 D3 D1 GND

LAH6

D17 D15 D13 D11 D9 D7 D5 D3 D1 GND

2 4 6 8 10 12 14 16 18 20

LRESET# LSERR# BTERM# WAIT# BLAST# LHOLDA LD31 LD29 LD27

LRESET# LSERR# BTERM# WAIT# BLAST# LHOLDA

3,6,12 3,10 3,4,6,11 3,6,12 3,4,6,11 3,4

LD24 LD22 LD20 LD18 LD16 LD14 LD12 LD10

1 3 5 7 9 11 13 15 17 19

+5V D16 D14 D12 D10 D8 D6 D4 D2 D0

D17 D15 D13 D11 D9 D7 D5 D3 D1 GND

2 4 6 8 10 12 14 16 18 20

LD25 LD23 LD21 LD19 LD17 LD15 LD13 LD11

B

B

2.5VCC

C 0

Logic Analyzer Header

R123

3.3VCC LED5

LED8

TP11

C

1

R122

TP10

C

1

0 PCIE12VCC

TP9

1

Logic Analyzer Header

LED6

LED

LED

LED R127 100

R124 1.2K

R125 330

A

A

PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com Title

Test Headers

5

4

3

2

Size Custom

Document Number

Date:

Wednesday, December 14, 2005

Rev 000

91-0058-000-A Sheet 1

5

of

15

A

B

C

D

E

4

4

PLX Option Module Connector

3.3VCC

5VCC

5VCC

R128 should not be installed by default 3,5,9 USERo/LLOCKo# 3,4,5,11 3

LBE#0 LBE#1 LBE#2 LBE#3 PB7

3,5,9 3,5,12 4 4 3,5,12

LINTo# LINTi# LBR0 LBG0 WAIT# POM_CS#

2

J3

POM_CLK

POM_CLK

3,4,5,12 3,4,5,12 3,4,5,12 3,4,5,12

J4

0_NP

ADS#

ADS#

3,4,5,11 BLAST# 3,5,9,10 USERi/LLOCKi# 3,4,5,12 LW/R# 3,4,5,12 READY# 3,5,12 LRESET#

3

USERo/LLOCKo# R128

BLAST# USERi/LLOCKi# R129 LW/R# READY# R130 LRESET#

0 0

LBE#0 LBE#1 LBE#2 LBE#3

WAIT# R132

0 LD31 LD30 LD29 LD28 LD27 LD26 LD25 LD24

LAD31 LAD30 LAD29 LAD28 LAD27 LAD26 LAD25 LAD24

LD23 LD22 LD21 LD20 LD19 LD18 LD17 LD16

LAD23 LAD22 LAD21 LAD20 LAD19 LAD18 LAD17 LAD16

LD15 LD14 LD13 LD12 LD11 LD10 LD9 LD8

LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LAD9 LAD8

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

ADS# DMAREQ0# GND DMAACK0# PCLK DMAEOT0# GND DMAREQ1# BLAST# DMAACK1# LOCK# DMAEOT1# W/R# USER0 GND USER1 POM_RDY_IN# 5 VCC RESET# 3.3 VCC BE0# 3.3 VCC BE1# ASYNC_SEL# BE2# PPC_ALE_H BE3# LABS2 SYNC_SEL# LABS3 GND 3.3 VCC IRQ_OUT# POM_SERR# IRQ_IN# 5 VCC POM_REQ DEN# POM_GNT DT/R# POM_WAIT# 3.3 VCC GND RD_STRB# 5 VCC RESERVED AD31 RESERVED AD30 POM_RDY_OUT# AD29 3.3 VCC AD28 3.3 VCC AD27 POM_PRESENT# AD26 BREQ_IN AD25 BREQ_OUT AD24 BTERM_IN# GND BTERM_OUT# AD23 5 VCC AD22 AD07 AD21 AD06 AD20 AD05 AD19 AD04 AD18 AD03 AD17 AD02 AD16 AD01 GND AD00 AD15 GND AD14 5 VCC AD13 3.3 VCC AD12 3.3 VCC AD11 GND AD10 EESDA AD09 EESCL AD08 +12V GND -12V

51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

DREQ0# DACK0# DMAEOT0# DREQ1# DACK1# DMAEOT1# USER0 USER1

DREQ0# DACK0# DMPAF/EOT# DREQ1# DACK1# PB1 PB2 PB3

1 2 3 4

3,4,5,11 3,4,5,10 3,4,5,11 3,4,5,12 3,4,5,11

+12V 5VCC

Molex 53109-0410

3

PB4 POM_CS#

R131 0 LA29

ALE

PB5 PB6

CS_0#

LA[31:2]

4 3,4,5,9,10,11,12

PB8 DEN# DT/R#

LA30 LA31 PB9 R133

READY#

0

PB10 0

R134 R135 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0

LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0

BREQi BREQo

READY#

3,4,5,12

BREQi BREQo BTERM#

3,5,9,11 3,5,9,11 3,4,5,11

0

2

+12V

PLX Option Module 1 (POM1)

2X50 Connector

3,4,5,9,10,11,12

LD[31:0]

1

1

PLX TECHNOLOGY, INC. 870 Maude Ave, Sunnyvale, CA 94085 www.plxtech.com Title

PLX Option Module Connector

A

B

C

D

Size Custom

Document Number

Date:

Wednesday, December 14, 2005

Rev 000

91-0058-000-A Sheet E

6

of

15

A

B

C

E

The components on this sheet are not installed by default.

Clock Circuit

3.3VCC

D

3.3VCC

2 R136 1 10_NP

X1/ICLK X2

1

2

10pF_NP

1

C94

7 13

2 2

R143 R142 49.9_NP 49.9_NP

R149 475 +/-1%_NP

ICS557-03 (Socket)

C95

49.9_NP

R138 49.9_NP

2 PETp0 2 PETn0

PETp0 PETn0

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47

1

3

2

1

25 MHz_NP

9

IREF

REFCLK2+ REFCLK2-

REFCLK+ 2 REFCLK- 2

1

4 5

CLK1p CLK1n

R147

1

SS0 SS1

CLK1p CLK1n

11 10

33_NP 1 1 33_NP

REFCLK+ REFCLK-

2

3 8

15 14

CLK0p CLK0n

J5 33_NP 1 1 33_NP

1

S0 S1

R137 2 2 R145 R148 2 2 R141

CLK0p CLK0n

2

1 2

PLACE R137,R138,R141,R142,R143,R145,R147,R148 CLOSE TO U12

U12

2

OE

0.01uF_NP

1

12 16 6

C93

2

0.01uF_NP

VDDODA VDDXD

R144 10K_NP 2 1 2 1 R139 R146 10K_NP 10K 2 1 2 1 R140 10K_NP XIN XOUT Y1 2

C92

GND GND

Internal pull-up resistor in OE, S0/1, SS0/1 R139,R140,R144,R146 NOT INSTALL

2

R641 10K_NP

1

4

1

4

10pF_NP

TX0+ TX0GND TX1+ TX1GND TX2+ TX2GND TX3+ TX3GND TX4+ TX4GND TX5+ TX5GND TX6+ TX6GND TX7+ TX7GND

GND RX0+ RX0GND RX1+ RX1GND RX2+ RX2GND RX3+ RX3GND RX4+ RX4GND RX5+ RX5GND RX6+ RX6GND RX7+ RX7-

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48

PERp0 PERn0

PERp0 PERn0

2 2

3

Midbus LAI

PCIE3.3VCC TP12

1

U13 C96 10uF_NP 2

2

C97 0.1uF_NP

8

VCC

OUT

5

4

GND

NC

1

CLK66

CLKIN R150

0_NP

CLKIN

3 2

osc_halfsize (socket)

1

1

Title

PCI Express Midbus & Clock Size B Date: A

B

C

D

Document Number

Rev 000

91-0058-000-A Wednesday, December 14, 2005

Sheet E

7

of

15

A

B

C

The components on this sheet are not installed by default.

PCIE3.3VCC 2.5VCC

FP1 B27

R161

0_NP

1 2 3 4 5 6 7 8 9 10

PA73 B35

R162

0_NP

F_TDI

R163

0_NP

D1

R160

0_NP

F_TMS R164

0_NP

F_TCK

R165

0_NP

A1

R166

0_NP

B4

R167

0_NP

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

20 19 18 17 16 15 14 13 12 11

R152

0_NP 2.5VCC

R153

0_NP USRVCC

R154

0_NP PCIE3.3VCC

R155

0_NP 2.5VCC

R156

0_NP USRVCC

R157

0_NP PCIE3.3VCC

R158

0_NP

R159

56_NP

9,13

144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Side A bus A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36

F_TDO D36

PA75 PA76 PA77 R168

R169

A[36:1]

PA72

PA78

PCIE3.3VCC

0_NP

D2 D1 C36

R171 R172

0_NP 100_NP

D36

R173

100_NP

F_TCK F_TDO F_TMS

C

JP6

TP20

1

0_NP

R170 100_NP

0_NP R632

R630

0_NP R633

0_NP

0_NP R631

B36

D[36:1]

PA74

20-pin SSOP, 0.025" pitch

3

Side D bus

1 3 5 7 9

F_TDI

2 4 6 8 10

2.5VCC

5VCC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Side C bus

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

144 Pin QFP Footprint

108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

C[36:1]

11,13

C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1

3

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

1 3 5 7 9 11 13

10,13

2

B[36:1]

0_NP R637

0_NP R636

0_NP R635

0_NP R634

2

4

FP2

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

JP7 2 4 6 8 10 12 14

12,13

D36 D35 D34 D33 D32 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1

R151

0_NP PCIE3.3VCC

E

144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109

Note this is designed for the Xilinx XCF01S or XCF02S device in their V020 package.

4

D

Side B bus

PCIE3.3VCC F_TDO USRVCC R174

R175

0_NP

0_NP

F_TDI U14 EZ117-2.5

F_TMS

C98

VIN

C99

1

+

GND

USRVCC 3

1

10uF_NP

VOUT

2 C100 + 10uF_NP

F_TCK

F_TDO

11

F_TDI

11

F_TMS

11

F_TCK

11

C101 0.01uF_NP

1

0.1uF_NP

Title

FPGA Footprint Size B Date: A

B

C

D

Document Number

Rev 000

91-0058-000-A

Wednesday, December 14, 2005

Sheet E

8

of

15

A

B

C

D

E

The components on this sheet are not installed by default.

Side A bus 4

4

8,13

A[36:1] 1.5VCC PCIE3.3VCC R176

0_NP

2.5VCC

R177

0_NP

R179

0_NP

1.5VCC VA1 C102 2,5,11 3,4,5,6

LD0

3,4,5,6

LD1

3,4,5,6

LD2

3,4,5,6

R182

LBG1

3,4,5,6

LD4

3,4,5 8,13 3,5,6,11 3,4,5

3,4,5

3,4,5

0_NP A7

R234

GPIO0

R237 0_NP R241

LCLK_T

R244 0_NP

LA5 8,13

R200

R229

LA4

3,5,12

0_NP A6

R225 0_NP

3,5,6 USERo/LLOCKo#

0_NP A5

R198

R219 0_NP

LA20

2,5,10

0_NP A4

A9

LA2

3,5

R191

R214

BREQo

0_NP A2 0_NP A3

R203 0_NP

LA2

56_NPA1

R186

R196

LD3

4

3

R180

GPIO3

USERi/LLOCKi# 3,5,6,10 3,4,5,10 LA6 3,4,5,10

LA7

3,4,5,10

LA8

2,5,10 GPIO1 LD5

A8

3,4,5,6

LD6

A9

3,4,5

LA4

3,4,5

LA5

0_NP A10

A11

3,5,12

0_NP A13 0_NP A14

A15 0_NP A16

A17

LA21

LD7

3,4,5,6

LD8

3,4,5,6

LD9

3,4,5,6

LD10

3,4,5,6

LD11

3,5,6

LINTo#

0_NP A19

PCIE3.3VCC

0_NP A20

PCIE3.3VCC R183 0_NP

A21

R187 0_NP

A22

R192 0_NP

A23

VA10

R184

0_NP A21

R185

0_NP A21

R188

0_NP A22

VA5 R189

0_NP A22

R193

0_NP A23

R194

0_NP A23

USRVCC

R190

0_NP VA2

R195

0_NP

C103

2.5VCC 2.5VCC

10nF_NP R197

0_NP A24

R199

0_NP A25

R202

0_NP A26

VA11

A27

R206 VA8

R211 0_NP

R208

R216 0_NP

A29

R217

R228

0_NP A31

R233

0_NP A32

VA9 R236

0_NP A33

R240

0_NP A34

R242

0_NP A35

0_NP A29

2.5VCC

0_NP VA3

USRVCC

R223

0_NP A30

0_NP A12

R227

0_NP A12

R230

0_NP A13

VA3 R231

0_NP A13

R204

1.5VCC

R210

0_NP

USRVCC

R215

0_NP

R222

0_NP

R232

0_NP

R235

0_NP

0_NP A28

R218

0_NP A29

VA7 R224

0_NP A30

USRVCC

3

C104 10nF_NP

0_NP A11

R226

USRVCC

VA4 C105 10nF_NP

R238

R246

R213 R221

VA12

0_NP

0_NP A27

0_NP A9

0_NP A28

0_NP A11

A30

R207 VA2 R209

R212 R220

A8

0_NP A27

0_NP A9

A28

PCIE3.3VCC R201 VA6 VA1 R205 0_NP

A30

3,4,5,6

VA4 R178

10nF_NP

R181

8,13

A12

A19

A19

3,4,5,6

A18

A18

8,13

0_NP A15

R239

0_NP A15

VA4 R245

0_NP A17

R249

0_NP A18

0_NP A36

PCIE3.3VCC R243

0_NP

2.5VCC

R247

0_NP

R250

0_NP

VA5 C106 10nF_NP

2

2

PCIE3.3VCC R251

0_NP

2.5VCC

0_NP

R256 R261

VA7 C107

PCIE3.3VCC R252

0_NP

USRVCC

0_NP

R257 R262

0_NP

0_NP

2.5VCC

R269

0_NP

R271

0_NP

VA11 C112

0_NP

2.5VCC

0_NP VA9

R258 R263

0_NP

R266

0_NP

10nF_NP

PCIE3.3VCC R268

0_NP

2.5VCC

R270

0_NP

R272

0_NP

10nF_NP

PCIE3.3VCC R254

0_NP

2.5VCC

R259

0_NP

R264

0_NP

C109 1.5VCC

0_NP

10nF_NP

PCIE3.3VCC R267

VA8 C108

PCIE3.3VCC R253

10nF_NP

VA10 C110

PCIE3.3VCC R255

0_NP

2.5VCC

R260

0_NP

R265

0_NP

VA6 C111

10nF_NP

10nF_NP

VA12 C113 10nF_NP

1

1

Title

FPGA Side A resistor options Size B Date: A

B

C

D

Document Number

Rev 000

91-0058-000-A

Wednesday, December 14, 2005

Sheet E

9

of

15

A

B

C

D

E

The components on this sheet are not installed by default. Side B bus 8,13

B[36:1]

PCIE3.3VCC R273

0_NP

2.5VCC

R274

0_NP

R275

0_NP

4

4

VB1 C114 10nF_NP

3,4,5,9

LA6

3,5

LSERR#

3,4,5,6

LD12

2,5,11

GPIO2

4

CS_3#

3,4,5,9

LA7

3,4,5

LA9

3,4,5 3

LA10 8,13

3,4,5,9

LA8

3,4,5,6

LD15

3,4,5,6

LD16

3,4,5,6

2

LA16 LA17

3,4,5,6

R287

0_NP B3 3,5

LA19

R292

0_NP B4 3,4,5,6

LD22

R294

0_NP B5 3,4,5,6

LD23

R298 0_NP

B6 3,4,5,6

LD24

R305 0_NP

B7 3,4,5

LA10

R312 0_NP

B8 3,4,5,6

LD25

B9 2,5,9

GPIO1

B10

3,5

3,4,5,6

R282

LA18

B10

LD17 LD18 LD19

LD26

R338

0_NP B14 3,4,5,6

LD27

R340

0_NP B15

R343

0_NP B16 3,4,5,6

R346

0_NP B17 2,5,9

R349

USERi/LLOCKi# 0_NP3,5,6,9 B18

2.5VCC

0_NP

R356

1.5VCC

R362

0_NP B21

R289

0_NP B22

R293

0_NP B23

R295

0_NP B24

GPIO0

VB7 C120

VB10 R280

R284 R290

0_NP B4

0_NP B21

R285

0_NP

0_NP B21

2.5VCC

R286

0_NP

R291

0_NP

0_NP B4

VB13

VB6

VB11

VB2 C115 PCIE3.3VCC

VB2 R299

R301 0_NP

R306 R308

0_NP B26

R315

0_NP B27

VB12 R319

0_NP B25

R309

0_NP B26

R316

0_NP B27

R321

0_NP B28

PCIE3.3VCC R300

0_NP B6

R307

0_NP B7

R314

0_NP B9 0_NP B10

0_NP B24

R303

0_NP B25

1.5VCC

R304

0_NP

VB7 R310

0_NP B26

USRVCC

R311

0_NP

R317

0_NP B27

R318

0_NP

R322

0_NP B28

VB3 C116

2.5VCC 2.5VCC

10nF_NP

0_NP B9

R324

3

0_NP B10

USRVCC

R325

0_NP B29

R326

0_NP B29

PCIE3.3VCC R327

0_NP

R330

0_NP B30

VB8 R331

0_NP B30

2.5VCC

R332

0_NP

R335

0_NP

USRVCC B30

VB15

0_NP B31

VB4 R337

0_NP B32

R339

0_NP B33

R342

0_NP B34

R345

56_NPB35

R347

0_NP B36

2.5VCC

0_NP

R363

10nF_NP

R348

0_NP

R357

B13

VB4 C117

PCIE3.3VCC R341

0_NP

R344

0_NP

VB9

PCIE3.3VCC R352

0_NP

R297

0_NP B8

VB3 R320

B29

R329 0_NP R334

R302 0_NP B8

B28 R323

0_NP B24

0_NP B7

VB14 R313

R296 0_NP B6

B25

VB8 C121

PCIE3.3VCC R353

0_NP

2.5VCC

0_NP

R358 R364

0_NP

VB9 C122

R359

0_NP VB10

0_NP

2.5VCC

0_NP

R360 R365

10nF_NP

VB5 C118 10nF_NP

0_NP B36

PCIE3.3VCC R354

0_NP

10nF_NP

VB11 C123

PCIE3.3VCC R350

0_NP

2.5VCC

R355

0_NP

R361

0_NP

VB6 C119

2

10nF_NP

0_NP

10nF_NP

0_NP

USRVCC

2.5VCC

R370

0_NP

1.5VCC

R374

0_NP

VB12 C124 10nF_NP

USRVCC

1.5VCC PCIE3.3VCC R281

10nF_NP

10nF_NP R366

B19

0_NP B1

R288

DACK0# LD28

VB5 0_NP B1

1.5VCC

LA11

B13 3,4,5,6

0_NP

R283

B29

R333

PCIE3.3VCC R351

0_NP B20

8,13

0_NP B12 3,4,5,11

3,4,5,6

R279

B28

0_NP B11

B19 VB1 R278

8,13

R328

R336 0_NP

R276 0_NP

LA9

0_NP B2 3,5

B9

8,13 3,4,5

B1 3,4,5

R277 0_NP

R378

0_NP

R380

0_NP

PCIE3.3VCC R367

0_NP

2.5VCC

R371

0_NP

R375

0_NP

VB13 C125

R661

0_NP

PCIE3.3VCC R368

0_NP

2.5VCC

R372

0_NP

1.5VCC

R376

0_NP

10nF_NP

VB14 C126

PCIE3.3VCC R369

0_NP

2.5VCC

R373

0_NP

R377

0_NP

10nF_NP R379

VB15 C127 10nF_NP

0_NP

1

1

Title

FPGA Side B resistor options Size B Date: A

B

C

D

Document Number

Rev 000

91-0058-000-A

Wednesday, December 14, 2005

Sheet E

10

of

15

A

B

C

D

E

The components on this sheet are not installed by default. Side C bus 8,13

C[36:1]

PCIE3.3VCC R381

0_NP

2.5VCC

R382

0_NP

USRVCC

R383

0_NP

R384

0_NP

PCIE3.3VCC R392

0_NP

2.5VCC

R395

0_NP

USRVCC

R398

0_NP

R401

0_NP

4

VC1 C128

4

10nF_NP

3,4,5,10

LA11

3,4,5,6

LD29

3,4,5,6

LD30

3,4,5,6

LD31

3,4,5,6

ADS#

3,4,5,6

DACK1#

3,4,5

LA12 8,13

3,4,5,12 3

3,5

LA15 BIGEND# BLAST#

3,4,5,6

LA31

2,5,10

0_NP C1

R391

0_NP C2

R394

0_NP C3

R397

0_NP C4

LA29

2,5,9

GPIO3

8

F_TCK

8

F_TMS

8

F_TDO

R385

BREQi

3,4,5

LA12

3,5,12

PMEIN#

3,4,5,6

BTERM#

8

F_TDI

3

CCS#

R403

0_NP C6

R405

0_NP C7 3,4,5,6 DMPAF/EOT#

C8

R416

0_NP C9

R422

0_NP C10

R427

0_NP C11

R430

0_NP C12

R433

0_NP C13 0_NP C14

R439

0_NP C15

R442

0_NP C16

R445

0_NP C17

R450

0_NP C18

DREQ0#

3,4,5,12

LA13

3,4,5,12

LA14

3,5,12

LA22

DP0

3,5

DP1

3,5

DP2

3,5

DP3

3,4,5,6

LA30

3,4,5,12

R388 R393

0_NP C20

LA3

VC5 R389

R396

0_NP C22

R399

0_NP C23

R402

0_NP C24

R404

0_NP C25

R409

0_NP C26

0_NP C20

VC6

R424

0_NP C20

1.5VCC

0_NP C7

R407 R414 R420

C30

0_NP C32

R438

0_NP C33

VC13

R411

0_NP C8

0_NP C34

R444

0_NP C35

2.5VCC

R412

0_NP

VC3 R417

0_NP C9

0_NP C27

R415

USRVCC

R418

0_NP

0_NP C28

R421

R423

0_NP

0_NP C27 0_NP C28

R425

0_NP C29

R426

0_NP C29

R428

0_NP C30

VC8 R429

0_NP C30

2.5VCC

10nF_NP 3

USRVCC USRVCC PCIE3.3VCC R431

0_NP

2.5VCC

R434

0_NP

USRVCC

R437

0_NP

R440

0_NP

0_NP C17

R443

0_NP C16

VC5 R447

0_NP C17

0_NP C36

VC9

PCIE3.3VCC R448

0_NP

2.5VCC

R453

0_NP

USRVCC

R454

0_NP

R455

0_NP

PCIE3.3VCC R461

0_NP

2.5VCC

R467

0_NP

USRVCC

R473

0_NP

R479

0_NP

VC4 C131

R451

0_NP C18

R452

C36

0_NP C18

Note: LA30=DEN# (J Mode) Note LA29=ALE (J Mode), LA31= DT/R#(J Mode)

2

VC3 C130

10nF_NP

VC11 R446 R449

0_NP

2.5VCC

VC4

R441

PCIE3.3VCC R408 VC7

0_NP C8

0_NP C29

R435

PCIE3.3VCC

10nF_NP

0_NP C7

VC12

0_NP C28

0_NP C31

VC2 C129

PCIE3.3VCC

0_NP C27

R432

C23

VC2

R410 R419

R390

1.5VCC

R406 R413

0_NP C1

0_NP C21

C30

3,5

VC11

VC10

3,4,5,6

8,13

0_NP C19

VC1 R387

0_NP C5

R436

GPIO2

3,5,6,9

R400

C8

3,4,5,6

3,4,5,6

R386

VC5 C132 10nF_NP

PCIE3.3VCC R456

0_NP

2.5VCC

R462

0_NP

USRVCC

R468

0_NP

VC7 C133

PCIE3.3VCC R457

0_NP

2.5VCC

R463

0_NP

USRVCC

R469

0_NP

10nF_NP 0_NP

R475

0_NP

PCIE3.3VCC R480

0_NP

PCIE3.3VCC R481

0_NP

2.5VCC

R482

0_NP

2.5VCC

R483

0_NP

USRVCC

R484

0_NP

USRVCC

R485

0_NP

R487

0_NP

10nF_NP R486

0_NP

0_NP

2.5VCC

R464

0_NP

USRVCC

R470

0_NP

10nF_NP

R474

VC12 C139

VC8 C134

PCIE3.3VCC R458

R476

0_NP

PCIE3.3VCC R459 VC9 2.5VCC C135 USRVCC 10nF_NP

R465

0_NP

R471

0_NP

R477

PCIE3.3VCC R460

0_NP

VC10 2.5VCC C136 USRVCC 10nF_NP

R466

0_NP

R472

0_NP

VC11 C137 10nF_NP

R478

0_NP

0_NP

0_NP

2

VC6 C138 10nF_NP

VC13 C140 10nF_NP

1

1

Title

FPGA Side C resistor options Size B Date: A

B

C

D

Document Number

Rev 000

91-0058-000-A

Wednesday, December 14, 2005

Sheet E

11

of

15

A

B

C

D

E

The components on this sheet are not installed by default. Side D bus 8,13

D[36:1]

4

PCIE3.3VCC R488

0_NP

2.5VCC

R489

0_NP

USRVCC

R490

0_NP

R491

0_NP

PCIE3.3VCC R501

0_NP

2.5VCC

R506

0_NP

USRVCC

R509

0_NP

R512

0_NP

4

VD1 C141 10nF_NP

3,4,5,11

LA15

3,5,9

LA21

3,5

LA23

3,4,5,6 DREQ1# 4

LBR1

3,5

LA24 8,13

3,4,5,11

0_NP D1

R497

0_NP D2

R502 R507

0_NP D4

R510

0_NP D5

R513

LA14

R523 R530

0_NP D6

D7

3,5 3,5 3,5,11 3,4,5,6 3,5,6 3,5,6 3,4,5,6 3,4,5,6

2

LA26 LA22 LD13 LINTi# LRESET# LBE#0 LBE#1

R542 R548 R554

3,4,5,6 LW/R# 3,4,5,6

LD14

3,4,5,6 READY# 3,4,5

LA28

0_NP D9

3,4,5

LA28

D10 0_NP D11 0_NP D12 0_NP D13

R563

0_NP D15

R568

0_NP D16 0_NP D17 0_NP D18

R496 D21

LA3

0_NP D14

R578

8,13

3,4,5,11

R558

R573

LCLK_T

0_NP D8

D10 LA25

3,5,9

D19

3,5,6

3

8,13

8,13

0_NP D3

D7 LA13

3,4,5,11

R493

WAIT#

3,5

LA27

3,4,5,6

LBE#2

3,4,5,6 3,5,11

PCIE3.3VCC R580

0_NP

2.5VCC

R585

0_NP

USRVCC

R590

0_NP

R595

0_NP

LBE#3 PMEIN#

VD7 C146

0_NP

2.5VCC

0_NP

R606

1.5VCC

R611

VD11 C151

R511

0_NP D24

R516

0_NP D25

R616

0_NP

R620

0_NP

0_NP D2

R499

0_NP D2

0_NP D3

R504

D19 1.5VCC

R521

0_NP D26

0_NP D6

R519 0_NP D27

R533

0_NP D28

1.5VCC

R515 R520

0_NP D7

R525

0_NP D8

VD12 VD11 R531

0_NP D27

R534

0_NP D28

R539

0_NP D29

R545

0_NP D30

0_NP D9

R537

VD3 R532

0_NP D10

R538

D29 R543

0_NP D11

D30

R544 VD13

R549

PCIE3.3VCC 0_NP D25

VD6 R527

0_NP D12

R550

PCIE3.3VCC R522

0_NP

2.5VCC R528

0_NP D27

2.5VCC

R529

0_NP

R535

0_NP D28

1.5VCC

R536

0_NP

R540

0_NP D29

USRVCC

R541

0_NP

VD7 R546

0_NP D30

R547

0_NP

R553

0_NP D31

0_NP D9

VD3 C143

2.5VCC 3

10nF_NP

0_NP D10 0_NP D11

USRVCC

0_NP D12

USRVCC

R551

0_NP D31

R552

0_NP D31

R555

0_NP D32

R556

0_NP D32

R557

0_NP D32

R559

0_NP D33

R560

0_NP D33

R561

0_NP D33

PCIE3.3VCC R562

0_NP

R564

0_NP D34

R565

0_NP D34

VD8 R566

0_NP D34

2.5VCC

R567

0_NP

R569

0_NP D35

R570

0_NP D35

R571

0_NP D35

USRVCC

R572

0_NP

R574

0_NP D36

R575

0_NP D36

R576

0_NP D36

R577

0_NP

PCIE3.3VCC R579

0_NP

2.5VCC

R584

0_NP

USRVCC

R589

0_NP

R594

0_NP

PCIE3.3VCC R599

0_NP

2.5VCC

R600

0_NP

1.5VCC

R605

0_NP

USRVCC

R610

0_NP

R615

0_NP

VD4

VD14

PCIE3.3VCC

0_NP D6

R518

0_NP D8

VD2 C142 10nF_NP

0_NP D25

0_NP D7

R524 R526

0_NP D3

VD2 R517

D13

VD4 C144 10nF_NP

PCIE3.3VCC R581

0_NP

2.5VCC

R586

0_NP

USRVCC

R591

0_NP

R596

0_NP

VD8 C147

PCIE3.3VCC R582

0_NP

2.5VCC

R587

0_NP

USRVCC

R592

0_NP

R597

0_NP

10nF_NP

PCIE3.3VCC R602

0_NP

2.5VCC

0_NP

R607 R612

VD12 C152

PCIE3.3VCC R603

0_NP

2.5VCC

0_NP

R608 R613

R617

0_NP

R621

0_NP

VD13 C153

0_NP

2.5VCC

R588

0_NP

USRVCC

R593

0_NP

R598

0_NP

PCIE3.3VCC R604

0_NP

2.5VCC

0_NP

R609 R614

0_NP

R619

0_NP

10nF_NP R618

0_NP

VD10 C149

VD5 C145 2

10nF_NP

10nF_NP

USRVCC

0_NP

10nF_NP USRVCC

VD9 C148

PCIE3.3VCC R583

10nF_NP

USRVCC

0_NP

10nF_NP USRVCC

R498

R514

1.5VCC

0_NP

0_NP D1

VD10

10nF_NP

PCIE3.3VCC R601

VD1 R495

R503 0_NP D23

D30

LD21

0_NP D1

D21

R508

8,13

3,4,5,6

R494

0_NP D20

0_NP D22

D29

LD20

VD5 VD9

R505

8,13

3,4,5,6

D19

VD14 C154

VD6 C150 10nF_NP

10nF_NP

1

1

Title

FPGA Side D resistor options Size B Date: A

B

C

D

Document Number

Rev 000

91-0058-000-A

Wednesday, December 14, 2005

Sheet E

12

of

15

A

B

C

D

E

The components on this sheet are not installed by default. 4

4

8,9

3

2

A[36:1]

8,10

B[36:1]

8,11

C[36:1]

8,12

D[36:1]

PF1

A1

PF19

A19

PF37

B1

PF55

B19

PF73

C1

PF91

C19

PF109

D1

PF127

D19

PF2

A2

PF20

A20

PF38

B2

PF56

B20

PF74

C2

PF92

C20

PF110

D2

PF128

D20

PF3

A3

PF21

A21

PF39

B3

PF57

B21

PF75

C3

PF93

C21

PF111

D3

PF129

D21

PF4

A4

PF22

A22

PF40

B4

PF58

B22

PF76

C4

PF94

C22

PF112

D4

PF130

D22

PF5

A5

PF23

A23

PF41

B5

PF59

B23

PF77

C5

PF95

C23

PF113

D5

PF132

D23

PF6

A6

PF24

A24

PF42

B6

PF60

B24

PF78

C6

PF96

C24

PF114

D6

PF131

D24

PF7

A7

PF25

A25

PF43

B7

PF61

B25

PF79

C7

PF97

C25

PF115

D7

PF133

D25

PF8

A8

PF26

A26

PF44

B8

PF62

B26

PF80

C8

PF98

C26

PF116

D8

PF134

D26

PF9

A9

PF27

A27

PF45

B9

PF63

B27

PF81

C9

PF99

C27

PF117

D9

PF135

D27

PF10

A10

PF28

A28

PF46

B10

PF64

B28

PF82

C10

PF100

C28

PF118

D10

PF136

D28

PF11

A11

PF29

A29

PF47

B11

PF65

B29

PF83

C11

PF101

C29

PF119

D11

PF137

D29

PF12

A12

PF30

A30

PF48

B12

PF66

B30

PF84

C12

PF102

C30

PF120

D12

PF138

D30

PF13

A13

PF31

A31

PF49

B13

PF67

B31

PF85

C13

PF103

C31

PF121

D13

PF139

D31

PF14

A14

PF32

A32

PF50

B14

PF68

B32

PF86

C14

PF104

C32

PF122

D14

PF140

D32

PF15

A15

PF33

A33

PF51

B15

PF69

B33

PF87

C15

PF105

C33

PF123

D15

PF141

D33

PF16

A16

PF34

A34

PF52

B16

PF70

B34

PF88

C16

PF106

C34

PF124

D16

PF142

D34

PF17

A17

PF35

A35

PF53

B17

PF71

B35

PF89

C17

PF107

C35

PF125

D17

PF143

D35

PF18

A18

PF36

A36

PF54

B18

PF72

B36

PF90

C18

PF108

C36

PF126

D18

PF144

D36

3

2

1

1

Title

PADS Size B Date: A

B

C

D

Document Number

Rev 000

91-0058-000-A

Wednesday, December 14, 2005

Sheet E

13

of

15

A

B

C

D

E

FP3 PF145 PF146 PF147 PF148 PF149 PF150 PF157 PF159 PF161 PF163 PF166 PF168 PF170 PF172

4

PF33 PF34 PF35 PF36 PF37 PF38 PF39 PF40 PF41 PF42 PF43 PF44 PF45 PF46

1 2 3 4 5 6 7 8 9 10 11 12 13 14

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

PF60 PF59 PF58 PF57 PF56 PF55 PF54 PF53 PF52 PF51 PF50 PF49 PF48 PF47

28 27 26 25 24 23 22 21 20 19 18 17 16 15

PF151 PF152 PF153 PF154 PF155 PF156 PF158 PF160 PF162 PF164 PF165 PF167 PF169 PF171

20X10 0.1" c-c Through hole Prototype Area

4

28-pin SOIC, 0.05" pitch

FP5 PF173 PF177 PF180 PF202 PF191 PF194 PF183 PF199 PF201 PF209 PF215 PF219 PF223 PF228 PF227 PF233 PF237 PF241 PF245 PF249 PF253 PF257 PF261 PF265

3

2

PF89 PF90 PF91 PF92 PF93 PF94 PF95 PF96 PF97 PF98 PF99 PF100 PF101 PF102 PF103 PF104 PF105 PF106 PF107 PF108 PF109 PF110 PF111 PF112

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

FP4 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

PF136 PF135 PF134 PF133 PF132 PF131 PF130 PF129 PF128 PF127 PF126 PF125 PF124 PF123 PF122 PF121 PF120 PF119 PF118 PF117 PF116 PF115 PF114 PF113

PF174 PF178 PF187 PF182 PF203 PF204 PF205 PF184 PF206 PF210 PF213 PF216 PF220 PF224 PF229 PF234 PF238 PF242 PF246 PF250 PF254 PF258 PF262 PF266

PF137 PF138 PF139 PF140 PF141 PF142 PF143 PF144 PF145 PF146 PF147 PF148 PF149 PF150 PF151 PF152 PF153 PF154 PF155 PF156 PF157 PF158 PF159 PF160

PF175 PF179 PF181 PF189 PF192 PF195 PF197 PF185 PF207 PF211 PF217 PF221 PF225 PF230 PF231 PF235 PF239 PF243 PF247 PF251 PF255 PF259 PF263 PF267

48-pin SSOP, 0.025" pitch

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

PF184 PF183 PF182 PF181 PF180 PF179 PF178 PF177 PF176 PF175 PF174 PF173 PF172 PF171 PF170 PF169 PF168 PF167 PF166 PF165 PF164 PF163 PF162 PF161

PF176 PF186 PF188 PF190 PF193 PF196 PF198 PF200 PF208 PF212 PF214 PF218 PF222 PF226 PF232 PF236 PF240 PF244 PF248 PF252 PF256 PF260 PF264 PF268

3

2

48-pin SSOP, 0.025" pitch

1

1

Title

Prototype Footprint Size B Date: A

B

C

D

Document Number

Rev 000

91-0058-000-A

Wednesday, December 14, 2005

Sheet E

14

of

15

A

B

C

D

E

4

4

U1B

3

2

T1 P1 W6 B12 B11 C11 B13 C8 B7 B9 R2 N3 M2 P3 V8 N2 T2 P2 N4 V7 R1 U2 Y6 E6 D4 C5 U4 R3 C10 D11 D5 E4

N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C

W7 U7 C4 C12

N/C N/C N/C N/C

PEX8311

N/C

C6

N/C N/C N/C N/C N/C N/C N/C N/C N/C

P4 U1 V5 V2 T3 T4 U3 V6 R4

N/C

A12

N/C N/C N/C N/C

A5 A6 B4 A4

N/C N/C N/C N/C

C7 A9 A7 B6

N/C N/C N/C N/C

D16 B8 B5 B3

3

2

1

1

Title

NC BALLS Size B Date: A

B

C

D

Document Number

Rev 000

91-0058-000-A

Wednesday, December 14, 2005

Sheet E

15

of

15

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